Power Ballast and Dual LED Driver for Automotive Front Lighting

The NCV78663 is a single−chip and high efficient smart Power ballast and Dual LED DRIVER designed for automotive front lighting applications like high beam, low beam, daytime running light (DRL), turn indicator, fog light, static cornering, and so on. The NCV78663 is a best fit for high current LEDs and provides a

The NCV78663 is a best fit for high current LEDs and provides a complete solution to drive two strings up to 60 V, by means of two internal independent buck switch channels, with a minimum of external components. For each channel, the output current and voltage can be customized

For each channel, the output current and voltage can be customized according to the application requirements. Diagnostic feature for automotive front lighting is provided on−chip. The device integrates a voltage booster controller, realizing a unique

The device integrates a voltage booster controller, realizing a unique input current filter with a limited number of externals. The NCV78663 can be used in stand−alone mode or together with a

The NCV78663 can be used in stand−alone mode or together with a companion microcontroller allowing maximum flexibility. Depending on the voltage and current of the connected LED string, the LED ballast parameters can be adapted by writing the SPI settings in the device, as such that no hardware changes are required. Features

Features • Single Chip Boost−Buck Solution

• Single Chip Boost−Buck Solution • Two Independent LED Strings Up to 60 V

• Two Independent LED Strings Up to 60 V • High Overall Efficiency

• Minimum of External Components • Active Input Filter with Low Current Ripple from Battery

• High Overall Efficiency • Minimum of External Components

• Active Input Filter with Low Current Ripple from Battery • Integrated Switched Mode Buck Current Regulator

• Integrated Switched Mode Buck Current Regulator • Two Integrated Buck Switches with 1.4 A Peak Current Capability

• Two Integrated Buck Switches with 1.4 A Peak Current Capability • Integrated Boost Controller

• Programmable Input Current Limitation • Average Current Regulation Through the LEDs

• Integrated Boost Controller • Programmable Input Current Limitation

• Average Current Regulation Through the LEDs • High Operating Switching Frequencies to Reduce Inductor Sizes

• SPI Interface for Optional External C and Dynamic Control of System Parameters • This is a Pb−Free Device

• Low EMC Emission for LED Switching and Dimming • SPI Interface for Optional External C and Dynamic Control of

• High Operating Switching Frequencies to Reduce Inductor Sizes • Integrated PWM Dimming with Wide Frequency Range

• DRL • Position or Park light

• This is a Pb−Free Device

• Static Cornering

• Low Beam • DRL

Typical Applications • High Beam

MARKING DIAGRAM

\

http://onsemi.com

A = Assembly Location WL = Wafer Lot

A = Assembly Location WL = Wafer Lot YY = Year

WW = Work Week G = Pb−Free Package

G = Pb−Free Package

ORDERING INFORMATION See detailed ordering and shipping information in the package

See detailed ordering and shipping information in the package dimensions section on page 36 of this data sheet.

NCV78663

Figure 1. Internal Block Diagram

NCV78663

PACKAGE AND PIN DESCRIPTION

Figure 2. Pin Connections

Table 1. PIN DESCRIPTION

NCV78663

Table 1. PIN DESCRIPTION

4. RSDO external resistor typical value is 1 k. An additional capacitor to ground (typically 47 pF) may be used in case of application noise observed.

5. External capacitors or RC may be added to these SPI lines for stable communication in case of application noise. The selection of these

6. As reported in the application diagram, the device pins TEST1 and TEST2 must be connected to ground.

7. For details about PCB layout, please refer to the dedicated section.

8. For details about PCB layout, please refer to the dedicated section.

9. RF1 and RF2 resistors typical value is 2.2 k and minimum required value is 1 k. It is recommended not to exceed a value of 22 k in order not to alter the VLED sampled value.

NCV78663

OPERATING CONDITIONS

Table 2. ABSOLUTE MAXIMUM RATINGS

^circ mathrm C,{}

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 6. Absolute maximum rating for pins: VBB, LEDCTRL1, LEDCTRL2.

6. Absolute maximum rating for pins: VBB, LEDCTRL1, LEDCTRL2.

7. Absolute maximum rating for pins: VBOOST, VBOOSTM3V, IBCK1SENSE+, IBCK1SENSE−, VINBCK1, VLED1, IBCK2SENSE+,

8. Absolute maximum rating for pins: VBOOST, VBOOSTM3V, IBCK1SENSE+, IBCK1SENSE−, VINBCK1, VLED1, IBCK2SENSE+, IBCK2SENSE−, VINBCK2, VLED2.

9. Absolute maximum rating for pins: TEST1, TEST2, VTEMP1, VTEMP2, DIAG1, DIAG2.

10. Absolute maximum rating for pins: TEST1, TEST2, VTEMP1, VTEMP2, DIAG1, DIAG2.

11. Absolute maximum rating for pins: VDRIVE, VGATE.

12. Absolute maximum rating for pins: VDRIVE, VGATE. 10.Absolute maximum rating for pins: SCLK, SCS, SDI, SDO.

13. Relative maximum rating for pins: VINBCK1, VINBCK2, IBCK1SENSE+, IBCK2SENSE+, IBCK1SENSE−, IBCK2SENSE− 12.Peak value. 13.Human Body Model (100 pF via 1.5 k, according to JEDEC EIA/JESD22−A114).

12.Peak value. 13.Human Body Model (100 pF via 1.5 k, according to JEDEC EIA/JESD22−A114).

14. A mission profile describes the application specific conditions such as, but not limited to, the cumulative operating conditions over life time, the system power dissipation, the system’s environmental conditions, the thermal design of the customer’s system, the modes, in which the device is operated by the customer, etc. 15.VBB = 13 V; Idrive = 10 mA

\mathsf{V}_{\mathsf B\mathsf{B},mathsfmathsf{Z A P}}

\ {\sf{T}}_{\sf{A}}

15.VBB = 13 V; Idrive = 10 mA 16.VBB = 13 V; Idrive = Q_gate x f_boost 17.Average value

17.Average value

NCV78663

Table 4. THERMAL RESISTANCE

ELECTRICAL CHARACTERISTICS

NOTE: Unless differently specified, all device Min & Max parameters boundaries are given for the full supply operating range and the junction temperature (TJ) range (-40;160) (°C).

(left({\ \mathord\\ {\ \ \ \ \ }}\ \right)

Table 5. VBB: BATTERY SUPPLY INPUT

Table 6. VDRIVE: 10 V SUPPLY FOR BOOST FET GATE DRIVE CIRCUIT

*Boost regulator must be active.

Table 7. VDD: 3 V LOW VOLTAGE ANALOG DIGITAL SUPPLY

NCV78663

Table 8. VBOOSTM3V: HIGH SIDE AUXILIARY SUPPLY

Table 9. OSC4M: SYSTEM OSCILLATOR CLOCK

Table 10. ADC FOR MEASURING VBOOST, VBB, VLED1, VLED2, VTEMP/AGP1, VTEMP/AGP2

NCV78663

Table 11. BOOSTER

18.For further details about the booster table and definitions, please refer to the related section contained in this datasheet.

Table 11. BOOSTER (continued)

NCV78663

Table 11. BOOSTER (continued)

Table 12. BOOSTER PRE−DRIVER

Table 13. BOOSTER − CURRENT LIMITATION

Table 14. ON−CHIP TEMPERATURE SENSOR Name Symbol

\mathsf{A t},\mathsf{T}{}_{\mathsf{J}}=160\ {}^{\circ}\mathsf{C}

NCV78663

Table 16. BUCK REGULATOR − CURRENT REGULATION

T_{j}=155^{\circ}C

1.9,\lor\leq\lor\ \ {sf L L E<22.6,V\lor}

-45^{\circ}\mathbb{C}{<}\mathbb{T}{<}155^{\circ}\mathbb{C}

\mathsf{V L E D}<1.9,\mathsf{V}

NCV78663

Table 17. 5 V TOLERANT DIGITAL INPUTS (CSB, SDI, SCLK)

\mathsf{T p}

\mathsf{R}_{\mathsf{p u l l}}\left(\mathsf{N o t e}\ 19\right)

19.Pull down resistor (Rpulldown) for SDI and SCLK, pull up resistor (Rpullup) for CSB.

Table 18. 5 V TOLERANT OPEN−DRAIN DIGITAL OUTPUT (SDO)

\mathsf{T p}

1_{\sf O D O0t t t}=-10,\sf m A

\mathsf{R_{D S(o n)_D D G}}

Table 19. 3 V TOLERANT DIGITAL INPUTS (TEST1, TEST2)

\mathsf{R}_{\mathsf p u l l d o w n}

Table 20. 3 V PUSH−PULL DIGITAL OUTPUTS (DIAG1, DIAG2)

\mathbf{T y p}

1_{\sf O I A G_o u t}=10,{\sf m A}

Table 21. 40 V TOLERANT DIGITAL INPUTS (LEDCTRL1, LEDCTRL2)

\ \mathrm V{{\bf{B}}}

NCV78663

Table 22. DIMMING INTERFACE

NCV78663

Table 23. SPI INTERFACE

Figure 5. SPI Timing

NCV78663

DETAILED OPERATING AND PIN DESCRIPTION

SUPPLY CONCEPT IN GENERAL Low operating voltages become more and more required

Low operating voltages become more and more required due to the growing use of start stop systems. In order to

respond to this necessity, the NCV78663 is designed to support power−up with a minimum guaranteed VBB = 5 V.

{\bf V}_{\mathrm{B B}}=5\ {\bf V}.

Figure 6. Cranking Pulse (ISO7637−1): System has to be Fully Functional (Grade A) from Vs = 5 V to 28 V

VDRIVE Supply The VDRIVE supply voltage is the primary supply for the

\ _s55

The VDRIVE supply voltage is the primary supply for the complete chip and sustains the VREG3V (which provides the VDD voltage, used by the internal circuitry) and the BOOST PREDRV, which generates the VGATE, used to switch the booster MOSFET. In order to support low VBB battery voltages and long

In order to support low VBB battery voltages and long crank pulse drops, the VDRIVE supply takes its energy from the source with the highest output voltage, either from: ♦ the VREG10V supply, which derives its energy

♦ the VREG10V supply, which derives its energy from the VBB input. ♦ the VBOOST_AUXSUP, which gets its energy from

Note: Powering the device via the VBOOST_AUXSUP will produce an extra power dissipation linked to the related linear drop (VBOOST−VBOOST_AUXSUP), which must be taken into account during the thermal design.

♦ the VBOOST_AUXSUP, which gets its energy from the VBOOST path. Under normal operating conditions, VREG10V is the

the VBOOST path. Under normal operating conditions, VREG10V is the highest and all the internal device plus gate driver energies are supplied via VBB. At power−up, the VREG3V (for VDD) is supplied

\mathrm{V B B}\geq5;\mathrm{V}

At power−up, the VREG3V (for VDD) is supplied through the VREG10V from the VBB input pin. Due to the low drop−out, the chip starts up from VBB ≥ 5 V and, the boost voltage starts to build−up. In case VBB drops below the regulator margin of

VDD Supply The VDD supply is the low voltage digital and analog

The VDD supply is the low voltage digital and analog supply for the chip and takes energy from VDRIVE. Due to the low drop−out regulator design, VDD is guaranteed already from low VDRIVE voltages (see Table 7). The Power On Reset circuit (POR) monitor is based on the VDD voltage.

VBOOSTM3V Supply The VBOOSTM3V is the high side auxiliary supply for

The VBOOSTM3V is the high side auxiliary supply for the gate drive of the buck regulators’ integrated high−side P−MOSFET switches. This supply receives energy directly from the VBOOST pin.

INTERNAL CLOCK GENERATION Two internal clocks are fully internally generated without

INTERNAL CLOCK GENERATION Two internal clocks are fully internally generated without the need for any further trimming by the user. Their accuracy is guaranteed under full operating conditions and independent from external component selection.

OSC16M Clock The OSC16M clock is the booster reference clock. It is

OSC16M Clock The OSC16M clock is the booster reference clock. It is factory trimmed and user selectable between typical 11.5 MHz and 22 MHz. The booster PWM frequency is 1/64 of the OSC16M frequency, thus between 179.7 kHz and 343.8 kHz. Refer to Table 11 for accuracy details.

ADC

General The built−in analog to digital converter (ADC) is an 8−bit

The built−in analog to digital converter (ADC) is an 8−bit capacitor based successive approximation register (SAR). This embedded peripheral can be used to provide the

This embedded peripheral can be used to provide the following measurements to an external Micro Controller Unit (MCU): VBOOST voltage

♦ VBOOST voltage VBB voltage

♦ VBB voltage VLED1, VLED2 voltages

♦ VLED1, VLED2 voltages VTEMP_AGP1, VTEMP_AGP2 voltages

♦ VTEMP_AGP1, VTEMP_AGP2 voltages The internal NCV78663 ADC state machine samples all

The internal NCV78663 ADC state machine samples all the above channels automatically, taking care for setting the analog MUX and storing the converted values in memory. The device LED diagnostics and the digital boost controller make use of the values as inputs. To remark that the VLEDx (1, 2) lines are sampled only

To remark that the VLEDx (1, 2) lines are sampled only when the respective LED output is activated and the last sampled value is kept, until it is overwritten (refreshed) by a new one. An external MCU can read−out all measured values via

An external MCU can read−out all measured values via the SPI interface in order to take application specific decisions. Please note that the MCU SPI commands do not interfere with the internal ADC state machine sample and conversion operations: the MCU will always get the last available data at the moment of the register read. Each new boost voltage sample occurs at 17 s worst case

Each new boost voltage sample occurs at 17 s worst case rate. VLED1 and VLED2 voltages are typically sampled at a rate of about 52 s (when the buck switches are on), while VTEMP_AGP1 and VTEMP_AGP2 are continuously sampled at a rate of 4 ms. The battery voltage is sampled typically each 108 s. ADC Channel Selection

ADC Channel Selection The ADC channel selection readout is done via the

The ADC channel selection readout is done via the SPI-CR11 register (the part “ADC_Sel” behaves as a pointer to the requested data), while the SPI−SR3 registers will hold the data (see section SPI Address Map). When polling the same channel over time, there is no need to refresh the address field, as the SPI−SR3 register will be automatically refreshed with the latest available data.

Battery Voltage ADC Measurement The battery voltage is sampled making use of the device

The battery voltage is sampled making use of the device supply VBB−pin. This measurement is also used by the boost controller for the closed loop voltage regulation to set the maximum duty cycle depending on the battery level: the lower the level, the higher the maximum duty cycle allowed. The (8 bit) conversion ratio is 40/255 (V/dec) =

lower the level, the higher the maximum duty cycle allowed. The (8 bit) conversion ratio is 40/255 (V/dec) = 0.157 (V/dec) typical. The external MCU can make use of the measured VBB value to monitor the status of the module supply and also for a different or more complex power de−rating algorithm than the one embedded in the NCV78663 (see Section Automatic Power De−rating). LED String Voltage ADC Measurement

LED String Voltage ADC Measurement The voltage at the pins VLEDx (1, 2) is measured. Their

The voltage at the pins VLEDx (1, 2) is measured. Their 8 bit conversion ratio is 80/255 (V/dec) = 0.318 (V/dec) typical. This is also used by the diagnostics controller to detect

This is also used by the diagnostics controller to detect OpenLEDx, ShortLEDx and IndShortLEDx. The external MCU can use the measured VLED value for

The external MCU can use the measured VLED value for a dedicated individual short LED algorithm, more complex than the threshold decision based embedded in the LED DRIVER.

LED Temperature Feedback / ADC General Purpose Inputs Measurement Measures the voltage at the pins VTEMP/AGPx (1,2).

Measures the voltage at the pins VTEMP/AGPx (1,2). The typical application would be sensing the transducer

The typical application would be sensing the transducer voltage related to LED modules’ temperature, so that the external MCU can use the information for protecting the LED strings from overheating, or to adapt the luminous flux to the temperature. A common technique is to use an NTC pulled up to the chip VDD. The VTEMP/AGPx typical sample rate is 4 ms. Please

The VTEMP/AGPx input dynamic range is given by the VDD voltage and no higher value can be forced to these pins.

NCV78663

Boost Voltage ADC Measurement This measure refers to the boost voltage at the

Boost Voltage ADC Measurement This measure refers to the boost voltage at the VBOOST−pin, with an 8bit conversion ratio of 80/255 (V/dec) = 0.318 (V/dec) typical. This measurement is also used by the boost controller and by the diagnostics controller to detect Boost under−voltage (BoostUV).

BOOST CONTROLLER The NCV78663 features one common booster stage for

The NCV78663 features one common booster stage for the two integrated buck current regulators. In addition, optional external buck regulators belonging to other devices can be cascaded to the same boost voltage source as well as exemplified in the picture below.

Figure 7. Cascade of Multiple NCV78663 Buck Channels on a Common Boost Voltage Source

current in case of LED strings PWM dimming. For nominal loads, the boost controller will regulate in continuous mode of operation, in order to maximize system power efficiency and to have the lowest possible input ripple current (with “continuous mode” it is meant that the supply current does not go to zero while the load is activated). In case of low loads or low dimming duty cycle values,

In case of low loads or low dimming duty cycle values, discontinuous mode can occur: this means the supply current

can swing from zero when the load is off to the required peak value when the load is on, while keeping the required input average current through the cycle. In such situations, the total efficiency ratio may be lower than the theoretical optimal. However, as also the total losses will at the same time be lower, there will be no impact on the thermal design.

The duty cycle (DC) is obtained internally out of a 6−bit counter (DC = 0 63). DC = 63 corresponds to duty cycle

The regulation feedback is mainly based on the VBOOST sampled value itself and only partially on the battery value seen at the device pin (VBB). Both signals are sampled by the NCV78663 internal ADC in the way described in the relative section. The boost voltage is regulated with a fixed frequency / variable duty cycle scheme. The duty cycle (DC) is obtained internally out of a 6−bit

Booster Voltage Range Selection The boost voltage can be programmed in one of the

The boost voltage can be programmed in one of the sixteen (16) available ranges by means of the SPI register booster output range [3:0] (or OTP in NCV78663 stand alone mode). Each of the ranges has its typical regulation level, called target (VBOOST_TRGT) and a so defined normal regulation region, or “window 1”, whose limits are NREGL and NREGH. In normal regulation mode, the boost voltage VBOOST

In normal regulation mode, the boost voltage VBOOST time average will always match the target, while its instantaneous value is free to swing between NREGL and NREGH. The absolute maximum voltage for each range is defined

The absolute maximum voltage for each range is defined as shutdown level (VSHUTDOWN). For VBOOST ≥ VSHUTDOWN, the MOSFET PWM (VGATE) will be switched off. The shutdown level can be chosen to minimize the needed voltage rating (size/cost) of the externals. The range should be selected with the appropriate NREG

The range should be selected with the appropriate NREG levels for the application. In particular, for proper operation of the LED strings, the selected boost voltage range “xx” must be such that NREGL_xx is higher than the maximum LED string voltage used. More information about the boost control loop is given in

Figure 8. NCV78663: Boost Voltage Regulation Closed Loop

More information about the boost control loop is given in the following section.

Booster Regulation Closed Loop Details The NCV78663 features a digital voltage mode controller

Booster Regulation Closed Loop Details The NCV78663 features a digital voltage mode controller designed to regulate the boost voltage around the target defined by the selected range. This closed loop system samples feedback signals and drives the boost MOSFET gate by PWM as shown in the next figure.

100% and DC = 0 corresponds to duty cycle 0%. However, 100% is never allowed and the maximum duty cycle corresponds to a parameter defined as DCmax. In addition, except in case of shutdown, the duty cycle is low−bounded to a value called DCmin, which is hard coded to value of “4” (4/63 = 6.3%) and is the same for all selectable booster ranges.

\mathbf{D C}_{\mathrm{m i n}}

NCV78663

DCmax is fetched from an internal ROM table and depends on the sampled battery voltage, this last divided in ranges. The general rule is the higher the battery voltage, the lower the DCmax allowed. This is intended to reduce boost voltage and input current overshoots when the battery voltage goes

\mathrm{D C_{m a x}}

\mathrm{D C_{m a x}}

\mathrm{D C_{m a x}}

too high. For low battery voltages, the DCmax is increased to permit more current inflow to allow achieving the required output power. The DCmax value 61 (96.8%) is never exceeded even in case of ultra−low battery. Eight battery ranges are available as shown below:

\mathrm{D C_{m a x}}

Eight battery ranges are available as shown below:

Table 24. NCV78663 BATTERY RANGES FOR BOOST CONTROLLER

0\div5,

10\div16V

16\div20V,

20\div24,

30\div35V

Each Vboost ADC sample is compared within voltage sections called “windows”. For each selected range, four different windows, plus a shutdown safety level, are present: A. Window 0. This is one of the “normal modes” of

A. Window 0. This is one of the “normal modes” of the control law. When the sampled Vboost falls in this region, there is no change in the PWM duty cycle. For all boost ranges, the width of this window is 2 V. The central value of this window is corresponding to VBOOST_TRGT, reported in the middle column of Table 11. B. Window 1. This is the most frequent status of the

B. Window 1. This is the most frequent status of the control law and this is what we refer to simply as general “normal mode”. When in this region, the PWM is corrected by “±1dec” (= ±1.58%) with a cadency corresponding to the boost control rate. The sign of the correction will be “plus” if the voltage is below window 0; “minus” otherwise. Each correction is intended to bring Vboost towards the VBOOST_TRGT. The size of any window 1, ranging in Table 11 from NREGL to NREGH, is typically about 10 V. C. Window 2. When in this region, the PWM duty is

\ {mathrm`}\pm1\mathrm{d e c}(=\pm1.58%)

C. Window 2. When in this region, the PWM duty is adapted by “±2” (= ±3.17%) with a cadency corresponding to the boost control rate, with the intention to bring Vboost towards the target. As the distance from the target is higher than in point B., the correction is stronger. D. Window 3. When in this range the controller

D. Window 3. When in this range the controller works in limitation mode. The PWM duty cycle is rapidly modified every two PWM periods: in the upper threshold, the duty cycle is decreased towards the DCmax trying to avoid reaching the shutdown level, whereas in the lower threshold side the duty cycle is ramped up towards the DCmin “pumping in” energy from the supply to avoid LED blank out because of lack of voltage headroom. E. Shutdown. This is a safety level to avoid

^{4}\pm2^{7},(=\pm3.17%)

\ \mathrm{:D C_{m a x}}

Table 11. Note: this “MAX rating” corresponds also to the maximum booster output voltage in case of unloaded stage (buck regulators off). A graphical explanation is given in the figure below by

A graphical explanation is given in the figure below by referring to boost range 06 as an example.

REMARKS and PRACTICAL CONSIDERATIONS For a well sized booster system with the NCV78663, the

For a well sized booster system with the NCV78663, the controller will operate inside window 1 (or window 0), thus:

\sf{V} {B O O S T_r R a T T}-\sf{s vee\nu}<\sf{V}{B O O s T}<\sf{V}_{B O O s T_r R a T T}+\sf{s}\ \sf{V}

An exception might be at booster load start−up, when its output power passes for the first time from zero (unloaded) to maximum (application target). In this case, the voltage is allowed to drop in the low threshold of window 3 and after a first settling transient, the regulation will enter normal mode (window 1).

NCV78663

Figure 10. NCV78663: Boost Voltage Possible Behavior at First Full Power Load Activation

In order to guarantee the regulation in WINDOW 1 throughout operating conditions and dimming, a total boost capacitance Cboost ≥ 50 F is recommended for medium to high application power. For further details about capacitance sizing, please refer to application notes. Please note that the boost voltage regulation loop is not

\geq50,\upmu\mathfrak{F}

Please note that the boost voltage regulation loop is not affected whether a continuous or discontinuous mode of operation (E.G. low dimming duty cycle) is taking place.

Booster PWM Frequency The booster controller is working with a constant

The booster controller is working with a constant frequency and variable duty cycle to control the booster voltage. The operating frequency is user selectable with three

The operating frequency is user selectable with three SPI/OTP setting bits (Section OSC16M Clock), in order to optimize the booster inductor’s size and EMC aspects.

Booster Disable Function In some cases, it is useful to disable the booster by means

♦ the NCV78663 uses a shared booster from another device, it is desired to start the hardware module from a

\mathrm{V_{L E D}}

External Boost FET Pre−driver The external boost MOSFET is directly controlled by the

♦ it is desired to start the hardware module from a complete off state, or to minimize energy consumption in some particular operating modes.

The external boost MOSFET is directly controlled by the integrated pre−driver with slope−control to attenuator EMC emissions. Due to the cycle by cycle current limitation, the peak−currents in the MOSFET are reduced, resulting in optimized system efficiency. Also for efficiency reasons, it is important to select a MOSFET with low gate−charge. The pre−driver is supplied by the VDRIVE supply

The pre−driver is supplied by the VDRIVE supply (typical 10 V) supporting standard FETs.

Figure 11. Buck Regulator Controlled Average Current

The buck regulator is the current source to the LED string. This block controls the peak current and also incorporates a constant ripple control circuit to ensure also stable average current through the LED string. The formula that defines the total ripple current over the

Buck Regulator The buck regulator is the current source to the LED string.

The formula that defines the total ripple current over the buck inductor is hereby reported: T (V V

\begin{array}{r l}{\Delta\mathsf{I} {\tt{B U C K_p k p p}}=\ }{{tttt}}&\frac{\mathsf{T}{\tt{F F F}}\times\ (\mathsf{V} {\tt{L E D}}+\mathsf{V}{\tt{D U O E E}})}\ {\ \

In the formulas above TOFF represents the buck switch off time, VLED is the LED voltage feedback sensed at the NCV78663 pin and LBUCK is the buck inductor value.

\mathrm{V_{L E D}}

NCV78663

\begin{array}{r}{\mathsf{f} {\tt B U B C K}=\frac{\mathsf{V}{\tt B O O S T}-\mathsf{V} {\tt L E D}}{\mathsf{V}{\tt B O O S T}}\cdot\frac{1}{\mathsf{T} {\tt O F F}}=}\ {=\frac{\mathsf{V}{\tt B O O S T}-\mathsf{V} {\tt L E D}}{\mathsf{V}{\tt B O O S T}}\times\frac{\mathsf{V} {\tt L E D}}{\mathsf{T}{\tt O F F}_{_\_V U C L}.}}}\end{array}

The buck average current is described by the formula:

\mathsf{I} {\mathsf{B U C K_p e a k}}=\frac{\mathsf{V}{\mathsf{T h r e s h o l d}}}{\mathsf{R}_{\mathsf{S E N S E}}},

Isf_{B U C K_A V G}=sf I I_{B U C K_p e a k}-\frac{\Delta I_{B U C K_p k p k}}{2}.

The parameter IBUCK_peak is programmable through the device by means of the internal comparator threshold (Table 16) over the external sense resistor RSENSE:

where Vthreshold is the current comparator internal set−point reference (Table 16).

\mathrm{V_{t h r e s h o l l}}

\begin{array}{c}{{\sf{V}} {\sf{T h r e s h o l d}}={\sf{V}}{\sf{T h r e s h o l d_M l N}}+{\sf{D e l t a_V_{r h r e s h o l d}}}\times}\ {{\ \\ \\ \\ \\ \\ times\ {u u r e e t_S e t i n g_\ P I P(d e c)}}.}\end{array}

The item “Current_setting_SPI (dec)” corresponds to the value written in the related for the “x” string, programmable from 0 to 127 (7bits). Please refer to Tables 26 and 27 for more information. The full buck circuit diagram follows:

The full buck circuit diagram follows:

Figure 12. Buck Regulator Complete Schematics

Independently from the peak current setting, there is also an overcurrent detection (fixed threshold) which is measured over the internal buck MOSFET. See Table 15. The LED average current in time is equal to the buck time

Figure 13. LED Current AC Components Filtered Out By the Output Impedance (scope snapshot)

For what concerns the LED ripple current, this is defined by the Buck inductor ripple current, the buck capacitor and

the total LED string equivalent impedance. A rule of thumb is to count a minimum of 50% ripple reduction by means of the capacitor CBUCK and this is normally obtained with a ceramic component ranging from 100 nF to 470 nF. The following figure reports a typical example. The use of CBUCK is a cost effective way to improve EMC performances without the need to increase the value of LBUCK, which would be certainly a more expensive action.

NCV78663

DIMMING The chip supports both analog and digital or PWM

The chip supports both analog and digital or PWM dimming. Analog dimming is done by controlling the LED current during operation. This can be done by means of changing the peak current level and/or the Toff_V constants (see Buck Regulator − Current regulation) by SPI commands.

In this section, we only describe the PWM dimming as this is the preferred method to maintain the desired LED color temperature for a given current rating. In digital dimming, the LED current waveform frequency

In digital dimming, the LED current waveform frequency is constant and the duty cycle is set according to the required light intensity. The two independent control inputs LEDCTRLx handle the dimming signals for the related channel. More details in the following section.

Dimming Control Scheme

Figure 14. NCV78663 Internal Digital (PWM) Dimming Structure

The dimming signal of each LED string is controlled via the respective LEDCTRLx input; the PWM there applied is sampled and converted into an output PWM signal used for enabling the buck channel driving the LEDx string (the internal buck MOSFET enabled signal is called BUCK_ENx). The BUCK_ENx signal frequency is obtained

The BUCK_ENx signal frequency is obtained multiplying the input frequency by the Dimming Frequency Factor (DFF). Increasing the dimming frequency is very useful to avoid the beats effect. In addition, higher dimming frequency reduce the dimming boost voltage swings for a given output booster capacitor. The BUCK_ENx duty cycle is equal to the input duty

given output booster capacitor. The BUCK_ENx duty cycle is equal to the input duty cycle times the internal scaling factors: the Dimming Duty Factor (DDF) and the Dimming Derating Factor (DRF). This last is automatically set by the device in case a power de−rating condition is occurring (see section Automotive Power De−rating). The DRF is applied to both channels simultaneously. The DDFx is instead individually programmable for each

\mathsf{D u t y F a c t o r_{x}=100\times\frac{255-D D F_{S P l_R E a x}}{255}}

\mathsf{D D F}_{\mathsf P P\__ E E G x}=255\times\frac{100-\mathsf{D u H y F a t o r r}{x}}{100}

or equivalently:

The following formula summarizes the effects on the dimming duty cycle for the LED STRING “x”: BuckENx DutyIN DutyFactor DRF

To detect an input duty cycle of 100% (“long one” = LEDx continuously ON), an input period higher than 40 ms is

\ {\sf u u c k E N x} {\sf D U T Y}=\ \sf{D u t y I N}{\sf L E D C T R I x}\times\ {\sf D u n y F a c t o r}_{x}\times\ {\sf D H F}

Where DutyINLEDCTRLx represents the input duty cycle provided by the external logic (or MCU) at the LEDCTRLx input. As the input signal at the LEDCTRLx is sampled by the

NCV78663

required. Vice versa, starting from a 100% duty cycle condition, in order to detect a 0% input signal (LEDx continuously OFF), up to 2 ms may be required. Using a 100% input duty cycle will by nature remove the

Using a 100% input duty cycle will by nature remove the external dimming frequency reference to the device. In such a case, if a duty cycle scaling (DDFx or DRF) is active, the internal frequency dimmer timer is used. Its base frequency is 500 Hz x DFF. This feature can be exploited as a method to avoid the use of an external frequency generator even when dimming is really intended: an hint for the application is then to tie (or pull up) the LEDCTRLx pins to the VBB pin and to set the wanted dimming parameters just by means of SPI. A DDFx = 0% (255dec) will always secure to turn off the LEDx strings across operating conditions. To note how the time resolution of both the input

To note how the time resolution of both the input LEDCTRLx sampler and the BUCK_ENx output reconstructed signals is 10 s nominal (see Table 22): this

value corresponds to the smallest resolution obtainable for digital dimming.

Automatic Power De−rating The LED output power can be automatically de−rated by

The LED output power can be automatically de−rated by decreasing the calculated output duty cycle in case of detected extreme conditions: either low battery voltage or active on−chip Thermal Warning. The NCV78663 features an embedded automatic power

The NCV78663 features an embedded automatic power derating function based on the battery voltage which can be enabled or disabled by OTP/SPI (PWRDERATE_DIS bit, see SPI map). The battery voltage measurement is automatically performed by the device sampling of the VBB pin. In case a protection diode in front of the VBB is used, its voltage drop and the discharge delay of the external capacitor in parallel to the pin have to be taken into account. The V_BAT power derating is implemented according to the graph below:

86%\times75%=

Figure 15. NCV78663 Internal V_Bat Power Derating Profile

simultaneously. In case of on−chip Thermal Warning, the calculated output duty cycle is further scaled to 75% of its previous calculated value (thermal derating). Then when the junction temperature falls below the Thermal Warning level, the thermal de−rating condition is automatically exited. The warning bit in SPI status register remains activated until reset via an SPI read−command. Example: V_Bat de−rating and thermal derating occurring

When the de−rating condition disappears the output duty will go back to 100% of the calculated output duty. The de−rating process is applied on both led channels simultaneously. In case of on−chip Thermal Warning, the calculated

SPI INTERFACE

The NCV78663 SPI transfer packet size is 16 bits. During an SPI transfer, the data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line (CLK) synchronizes shifting and sampling of the information on the two serial data lines: SDO and SDI.

The serial peripheral interface (SPI) is used to program the default start−up operating parameters in OTP via the ZAP! operation. Optionally, it allows an external microcontroller (MCU) to communicate with the device to read−out status information and to change operating parameters after power−up. The NCV78663 SPI transfer packet size is 16 bits. During an SPI transfer, the data is simultaneously transmitted

NCV78663

The DO signal is the output from the Slave, and the SDI signal is the output from the Master. A slave select line (CSB) allows individual selection of a slave SPI device in a time multiplexed multiple−slave system. The CSB line is active low. If an NCV78663 is not selected, SDO is in high impedance state and it does not interfere with SPI bus activities. Since NCV78663 always clocks data out on the

falling edge and samples data in on rising edge of clock, the MCU SPI port must be configured to match this operation. The SPI CLK idles low between transferred frames. The diagram below is both a master and a slave timing diagram since CLK, DO and DI pins are directly connected between the Master and the Slave.

Figure 16. NCV78663 SPI Transfer Format

Note: The data transfer from the shift register into the locally used registers, interpretation of the data is only done at the rising edge of CSB. The Data that is send over to the shift register to be

The Data that is send over to the shift register to be transmitted to the external MCU is sampled at the falling edge of CSB, just at the moment the transmission starts. The implemented SPI block allows interfacing with

edge of CSB, just at the moment the transmission starts. The implemented SPI block allows interfacing with standard MCUs from several manufacturers. When interfaced, the NCV78663 acts always as a Slave and it cannot initiate any transmission. The MCU is instead the master, able to send read or write commands. The NCV78663 SPI allows connection to multiple slaves by

means of both star connection (one individual CSB per Slave, while SDI, SDO, CLK are common) or by means of daisy chain (common CSB signal and clock, while the data lines are cascaded as in the figure). An SPI star connection requires a bus = (3 + N) total lines, where N is the number of Slaves used, the SPI frame length is 16 bits per communication. Regarding the SPI daisy chain connection, the bus width is always four lines independently on the number of slaves. However, the SPI transfer frame length will be a multiple of the base frame length so N x 16 bits per communication: the data will be interpreted and read in by the devices at the moment the CSB rises.

Transfer Format All SPI commands (to SDI pin of NCV78663) from the

The address/command byte is the MSB and is divided into two nibbles (2 x 4 bits). Each nibble is an address pointing to the 16 bytes address space of the NCV78663 SPI register map (see related section) and in the same time it is interpreted also as a command (explanation given below). Two types of registers exist in the SPI address space: Control and Status registers. Control registers are read/write

Figure 17. NCV78663 SPI Star vs. Daisy Chain Connection

SPI Daisy chain connection

accessible whereas Status registers are only read accessible. The type of the register is determined by the address decoder of the SPI and depends on its position in the address space. Three command−types can be distinguished: “Write to a

♦ Writing to a control register is accomplished only if the address of the target register appears in the upper address/command nibble. The contents of the data−byte will be copied in the control register.

NCV78663

♦ Reading from a control register is accomplished by putting its address in the lower address/command nibble. The data byte has no function for this command. ♦ Reading from a status register is accomplished by

command. ♦ Reading from a status register is accomplished by putting its address either in the upper or in the lower

address/command nibble. The data byte has no function for this command. The response (SDO) on the commands from the first

The response (SDO) on the commands from the first frame is always two bytes long and is located in the subsequent SPI frame. The possible combinations of SDI/SDO and their use are summarized in the following table:

Table 25. SPI FRAME FORMAT TRANSFER

LEGENDA: ACRx = Address of Control Register x

♦ ACRx = Address of Control Register x ASRx = Address of Status Register x

♦ ASRx = Address of Status Register x DICRx = Data Input of Control Register x

♦ DICRx = Data Input of Control Register x ♦ DOCRx/DOSRx = Data Output of corresponding Register.

♦ DOCRx/DOSRx = Data Output of corresponding Register. XXh = any byte

{\mathrm{X X h}}={\mathrm{a n y,b t e}}

SPI Command Example: Write “data value 255” (= 0xFF hex) to control register at “address 1” (= 0x01 hex) and read control register at “address 4” (= 0x04 hex)

255^{\circ},(=0x F\mathrm{,h e x})

1^{},(=0\0\ \mathrm01,\mathrm{h e x})

4^{\ },(=0\ \mathrm{x004,\ emathrm{x x}))

NOTE: In any SPI communication transfer a frame which is not multiple of 16 bits is considered as an error and is discarded by the device. In case of SPI error, the specific error flag in STATUS REGISTER 2 is raised (see SPI address map).

NCV78663

SPI ADDRESS MAP

Table 26. SPI BANK REGISTER SUMMARY

Mapped in both, SPI and OTP address maps (with different address)

*Registers with write possibility only in TEST mode (TEST1 pin = high) **Read−only registers as exception A detailed description of the SPI registers follows in the next section.

A detailed description of the SPI registers follows in the next section. 20.RevID = 7dec (= [111] bin) for QAA silicon, RevID =6dec (= [110] bin) for PAA silicon (register 0x0F).

20.RevID = 7dec (= [111] bin) for QAA silicon, RevID =6dec (= [110] bin) for PAA silicon (register 0x0F).

NCV78663

SPI REGISTERS DETAILS

NCV78663

NCV78663

NCV78663

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NOTE: Flags have “L” for latched information or “R” for real time information. All latched flags are “cleared upon read”.

NCV78663

OTP

Description The OTP (One Time Programmable) Memory contains

The OTP (One Time Programmable) Memory contains 109 bits; 37 bits are for trimming purposes and are programmed at the end of the silicon manufacturing line at ON Semiconductor. The remaining 72 bits are system dependent parameters and are user programmable via the SPI interface and the “ZAP!” operation: these should be considered as the power−up default operating parameters and are typically programmed at the end of the module manufacturing line. The OTP−bits, as the name suggests, can be programmed

The OTP−bits, as the name suggests, can be programmed only once. However, this is not a limiting factor as the system dependent parameters can be updated after power−up via the SPI−interface (the only two exceptions are the boost control rate and the DIAGx response mode, see OTP address map). The OTP Controller operates:

The OTP Controller operates:

1. either at Startup, to load the default values from

2. either at Startup, to load the default values from OTP to the SPI registers,

3. or when the chip is set in Test mode, to get full OTP access depending on the status of the OTPLock−bits.

The OTP memory is controlled via 2 SPI control registers (CR9 and CR10) and the TEST1−pin, which must be high during OTP operations.

OTP Interface The OTP memory is controlled via 2 SPI control registers

SPI−CR9 acts as the OTP Control register OTP_CTRL [7:0]:

Control Register

OTP_CTRL [7] START bit: Set of START bit starts execution of the selected command;

OTP_CTRL [6:5] Command to be executed. The CMD [1:0] list is reported in the table below;

Programming OTP or “Zap!” Set of OTP_Start bit starts execution of the selected command, written in OTP_CTRL [6:5] bits. At that very moment the OTP address to be accessed, written in OTP_CTRL [3:0] bits, is latched and is kept there until the operation finishes. When OTP state machine completes the command, it clears automatically OTP_Start bit. This allows monitoring the status of the operation by polling of the OTP_Start via SPI.

♦ When accessed for write (through the SPI), that register keeps the data to be used in a “Load OTP” operation ♦ When accessed for read (through the SPI), the data

Programming OTP or “Zap!” Set of OTP_Start bit starts execution of the selected

operation ♦ When accessed for read (through the SPI), the data is taken directly from the OTP registers.

♦ When accessed for read (through the SPI), the data is taken directly from the OTP registers.

default. The only exception is “Point to OTP Cell” command.

30^{\circ}\mathrm{C}

The bit OTPLockInt will be set at the end of the silicon manufacturing line at ON Semiconductor, after device trimming. By doing so, the factory trimming parameters can never be changed by the user as a safety feature.

OTP Lock To prevent unwanted OTP zapping, there is the possibility

NCV78663

User OTP Lock The bit OTPLockExt allows the user to protect the system

will be the system default parameters after power−up. We strongly recommend making use of this lock to avoid unwanted setting changes in the application and to keep TEST1 to GND.

Table 27. OTP ADDRESS MAP

Mapped in both, SPI and OTP address maps (same naming but different address)

*Only for ON Semiconductor trimming purpose. Locked if OTPLockInt−bit is set.

NCV78663

DIAGNOSTICS The NCV78663 offers a wide range of device−integrated

The NCV78663 offers a wide range of device−integrated diagnostic features. Their description follows.

Diagnostics Description • Thermal Warning: this mechanism detects a junction

• Thermal Warning: this mechanism detects a junction temperature which is close but lower to the chip maximum allowed, providing the information that some action is required to prevent overheating causing Thermal Shutdown. The thermal warning condition will automatically generate a power derating action by reducing the output duty cycle to 75% of the original value. See Section Automatic Power de−rating. • Booster reached maximum duty cycle: the booster

• Booster reached maximum duty cycle: the booster controller has set the maximum duty cycle to the gate PWM. This means that the booster is not capable to deliver the required energy to the output. Reasons could be either: ♦ input current limit is insufficient;

♦ input current limit is insufficient; input current line to the inductor or MOSFET open;

so that only after both TSD and TW real internal signals disappear, booster and buck converters will be again automatically enabled. This is done to make sure that device can recover also in stand−alone mode (no MCU or SPI Master in the system). The normal operation of booster and buck converters is restored only after the temperature drops below the TW level − thus providing hysteresis for the TSD recovery process. • Power derating warning: Indicates that the power

♦ input current line to the inductor or MOSFET open; ♦ too high load required by the booster and/or too low

• Thermal Shutdown: The junction temperature has reached the TSD level (see Table at 4.9). The booster and the LED outputs are immediately disabled to prevent device overheating. The TSD flag is latched in the SPI SR2 (State 2) register and stays set until the SR2 register is read by the SPI Master. On the other hand, booster and buck converters disable logic is using the real time TSD and TW signals (not the SPI flags),

• Power derating warning: Indicates that the power de−rating function has been activated. See Section Automatic Power De−rating. • SPI Error: SPI frame detected with a length not equal

• SPI Error: SPI frame detected with a length not equal to a multiple of 16 bits. • Boost under voltage error: Detects a boost under

• Boost under voltage error: Detects a boost under voltage by raising the related bit and lowering both DIAGx pins to zero. The Boost voltage error bit in SPI status register is cleared in case of being read or in case of longer than 50 ms low pulse at LEDCTRLx pin. A 50 ms low pulse on the LEDCTRLx releases the relative DIAGx pin as well. • Detection of ‘open’ LED−string: detects if the LED

• Detection of individual shorted LED: the absolute LED−string voltage is monitored and compared to an user−programmable threshold level:

• Detection of ‘open’ LED−string: detects if the LED output voltage has reached the reference minimum booster voltage for the specific range as defined in the table below. The DIAGx pin remains zero as long as low pulse longer than 50 ms is not detected at LEDCTRLx pin. The Open LED−string error bit in SPI status register is cleared in case of being read or in case of longer than 50 ms low pulse at LEDCTRLx pin.

Table 28. OPEN LOAD DIAGNOSTIC DETECTION LEVEL AND BOOST UNDERVOLTAGE DETECTION LEVELS

• Detection of ‘shorted’ LED−string: the corresponding error bit is set when the LED voltage is below the threshold level, fixed at 1.9V, with absolute ADC value 06hex typical. The DIAGx pin remains to low value until a low state longer than 50 ms is detected at LEDCTRLx pin. The short error bit in SPI status register is cleared in case of being read or in case of longer than 50 ms low level at LEDCTRLx pin. • Detection of individual shorted LED: the absolute

\sf{I n d S}h o o r h h e s_{X}[V]=80\times\frac{1\ {sf I}S n o r t T h r e s_{S P l_R R a x}(d e c)}{255}.

The default value is fixed in OTP and can be overwritten in a volatile register by a specific SPI command. If the LED−string voltage drops below that absolute level, the chips recognizes single or more shorted LEDs and the error bit is raised in the relative STATUS register (1 or 2). No specific action taken on the DIAGx pins based on this detection.

NCV78663

microcontroller, taking direct advantage of the measured LED voltage via the SPI interface. • Buck regulator over−current error (OCLEDx): this

• Buck regulator over−current error (OCLEDx): this error condition is triggered if the buck current is higher than the OCD level (see Table 15) for 16 consecutive buck periods and the responsible channel is switched off. The conditions for clearing the OCLEDx bits is reading the related SPI STATUSx or keeping LEDCTRLx = 0 for 50 ms.

Diagnostics Feedback Any error which leads to a non−functional LED string is

Any error which leads to a non−functional LED string is reported via the DIAGx (1, 2) pins. Each LED output driver has its own diagnostics output

Each LED output driver has its own diagnostics output DIAGx. Depending on the DIAGx response mode option

(OTP map register 0x0A − bit 7), the behavior of the DIAGx can be either “static” (default, bit = 0) or “pulsed” (bit = 1). In the default case, when the LEDx line is active, the DIAGx is continuously high, providing there is no error detected in the respective LEDx string. Otherwise, if the DIAGx response mode is programmed to “one”, the pulse starts typically at the beginning of LED turn−on and is one−shot high for a duration of 500 ms if no errors are detected. All LED string related errors and boost under voltage

All LED string related errors and boost under voltage error are latched and get cleared when the inputs (LEDCTRLx) are disabled for a time longer than 50 ms. The DIAGx is continuously low if there is any of the

The DIAGx is continuously low if there is any of the responsible errors detected in the respective LED string persists, as summarized in the Diagnostics Summary Table.

Table 29. DIAGNOSTICS SUMMARY TABLE

*...x = ...1 or ...2 \\ See Table 28

\\ See Table 28

NCV78663

PCB LAYOUT RECOMMENDATIONS

This section contains instructions for the NCV78663 PCB The areas which are most critical for a layout point of view layout application design. Although this guide does not are highlighted in the following picture: claim to be exhaustive, these directions can help the developer to reduce application noise impact and insuring the best system operation.

Figure 18. NCV78663: Application Critical Areas at PCB Level

Booster Current Limitation Circuit: AREA (A) C. The MOSFET’s dissipation area should be The booster limitation circuit relies on a low voltage stretched in a direction away from the sense comparator, which triggers with respect to the sense voltage resistor to minimize resistivity changes due to across the external resistor Rboost_sense. In order to heating; maximize power efficiency, the threshold voltage is set to a D. Possibly reduce to the least the distance between rather low value by design (typical 100 mV, see Table 13) Rboost_sense and the NCV78663 boost limitation and this area may be affected by the MOSFET switching comparator’s inputs (IBSTSENSE+ and noise if no specific care is taken. The following IBSTSENSE−); recommendations are given: E. If the current sense measurement tracks are

A. Use a four terminals current sense method as interrupted by series resistors or jumpers (once as depicted in the figure below. The measurement a maximum) their value should be matched and PCB tracks should run in parallel and as close as low ohmic (pair of 0 to 47 max) to avoid possible to each other, trying to have the same errors due to the comparator input bias currents; length. The number of vias along the measurement F. Avoid using the board GND as one of the path should be minimized; measurement terminals as this would also B. Place Rboost_sense sufficiently close to the introduce errors. MOSFET source terminal; ** http://onsemi.com**

NCV78663

Figure 19. Four Wires Sensing Method for Boost Current Limitation Comparator

Buck Current Comparators: AREAs (B1) and (B2) Vboost Related Tracks: AREA (C) The blocks (B1) and (B2) control the buck peak currents The three NCV78663 device pins VBOOST, by means, respectively, of the external sense resistors IBCK1SENSE+ and IBCK2SENSE+ must be at the same Rbuck_1_sense and R_buck_2_sense. As the regulation is individual voltage potential to guarantee proper functioning performed with a comparator, the considerations explained of the internal buck current comparator (whose supply rails in the previous section “Booster Current Limitation Circuit: are Vboost and VboostM3V). In order to achieve this target, AREA (A)” remain valid. it is suggested to make a PCB star track connection between In particular, the use of a four terminals current sense these three points close to the device pins. The width of the method is required, this time applied on (IBCK1xSENSE+, tracks should be large enough (>40 mils) and their length as IBCKxSENSE−). The sensing PCB tracks should be kept as balanced as possible (ideally all equal). short as possible, with the sense resistors close to the device, but preferably outside of its PCB heating area in order to limit measurement errors produced by temperature drifts.

Figure 20. PCB Star Connection Between Vboost, IBCK1SENSE+ and IBCK2SENSE+ (simplified drawing)

** http://onsemi.com**

NCV78663

GND Connection: AREA (D) The NCV78663 GND and GNDP pins must be connected

The NCV78663 GND and GNDP pins must be connected together. It is suggested to perform this connection directly close to the device, behaving also as the cross-junction

between the signal GND (all low power related functions) and the power GND (related to all power switching areas). The device exposed pad should be connected to the GND plane for dissipation purposes.

ORDERING INFORMATION

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

onsemi

SSOP36 EP CASE 940AB ISSUE A

DIMENSIONS: MILLIMETERS

DATE 19 JAN 2016

NOTES:

1. DIMENSIONING AND TOLERANCING PER

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.

ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR

2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE b DIMENSION AT MMC.
4. DIMENSION b SHALL BE MEASURED BE-

EXCESS OF THE b DIMENSION AT MMC. 4. DIMENSION b SHALL BE MEASURED BE- TWEEN 0.10 AND 0.25 FROM THE TIP. 5. DIMENSIONS D AND E1 DO NOT INCLUDE

TWEEN 0.10 AND 0.25 FROM THE TIP. 5. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. DIMENSIONS D AND E1 SHALL BE DETERMINED AT DATUM H. 6. THIS CHAMFER FEATURE IS OPTIONAL. IF

DETERMINED AT DATUM H. 6. THIS CHAMFER FEATURE IS OPTIONAL. IF IT IS NOT PRESENT, A PIN ONE IDENTIFIER MUST BE LOACATED WITHIN THE INDICAT- ED AREA.

GENERIC MARKING DIAGRAM*

XXXX = Specific Device Code A = Assembly Location

WL = Wafer Lot YY = Year

YY = Year WW = Work Week

WW = Work Week G = Pb−Free Package

onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

G = Pb−Free Package

onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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