Analog/Digital Dimmable
Power Factor Corrected
Quasi-Resonant Primary
Side Current-Mode

Analog/Digital Dimmable
Power Factor Corrected
Quasi-Resonant Primary

Side Current-Mode

Side Current-Mode
Controller for LED Lighting

Controller for LED Lighting

NCL30086BH

The NCL30086BH is a controller targeting isolated and
non−isolated “smart−dimmable” constant−current LED drivers.
Designed to support flyback, buck−boost, and SEPIC topologies, its
proprietary current−control algorithm provides near−unity power
factor and tightly regulates a constant LED current from the primary
side, thus eliminating the need for a secondary−side feedback circuitry
or an optocoupler.
Housed in the SOIC10 which has the same body size as a standard

or an optocoupler.
Housed in the SOIC10 which has the same body size as a standard
SOIC8, the NCL30086BH is specifically intended for very compact
space−efficient designs. The device is highly integrated with a
minimum number of external components. A robust suite of safety
protections is built in to simplify the design. To ensure reliable
operation at elevated temperatures, a user configurable current
foldback circuit is also provided. In addition, it supports analog and
PWM dimming with a dedicated dimming input intended to control
the average LED current.
Pin−to−pin compatible to the NCL30086, the NCL30086BH

Features
• Quasi−resonant Peak Current−mode Control Operation

• Quasi−resonant Peak Current−mode Control Operation
• Valley Lockout Optimizes Efficiency over the Line/Load Range

• Valley Lockout Optimizes Efficiency over the Line/Load Range
• Constant Current Control with Primary Side Feedback

• Constant Current Control with Primary Side Feedback
• Tight LED Constant Current Regulation of ±2% Typical

• Analog or PWM dimming
• Line Feedforward for Enhanced Regulation Accuracy

¨ Brown−Out Detection
¨ OVP on VCC

¨ Programmable Over Voltage / LED Open Circuit
Protection
¨ Cycle−by−cycle Peak Current Limit

\\mathrm{V\_{c c}}

• Power Factor Correction
• Analog or PWM dimming

¨ Winding Short Circuit Protection
¨ Secondary Diode Short Protection
¨ Output Short Circuit Protection

• Line Feedforward for Enhanced Regulation Accuracy
• Low Start−up Current (10 A typ.)

¨ OVP on VCC
¨ Programmable Over Voltage / LED Open Circuit

¨ Output Short Circuit Protection

SOIC−10
CASE 751BQ

MARKING DIAGRAM

A = Assembly Location
L = Wafer Lot

L = Wafer Lot
Y = Year

Y = Year
W = Work Week

¨ Current Sense (CS) Short Detection
¨ User programmable NTC Based Thermal Foldback

PIN CONNECTIONS

¨ User programmable NTC Based Thermal Foldback
¨ Thermal Shutdown
• −40 to 125°C Operating Junction Temperature

• −40 to 125°C Operating Junction Temperature
• Pb−Free, Halide−Free Product

• Integral LED Bulbs
• LED Light Engines

• LED Light Engines
• LED Driver Power Supplies

• LED Driver Power Supplies
• Smart LED Lighting Applications

• Smart LED Lighting Applications

* * *

NCL30086BH

Figure 1. Typical Application Schematic in a Flyback Converter

Figure 2. Typical Application Schematic in a Buck−Boost Converter

* * *

NCL30086BH

Table 1. PIN FUNCTION DESCRIPTION

| Pin No | Pin Name | Function | Pin Description |
| --- | --- | --- | --- |
| 1 | DIM | Analog/PWM Dimming | This pin is used for analog or PWM dimming control. An analog signal that can be varied between $ V\_{DIM0} $ and $ V\_{DIM100} $ or a PWM signal can be used to adjust the LED current. |
| 2 | ZCD | Zero Crossing Detection | Connected to the auxiliary winding, this pin detects the core reset event. |
| 3 | VS | Input Voltage Sensing | This pin monitors the input voltage rail for: |
| Power Factor Correction |  |  |  |
| Valley lockout |  |  |  |
| Brownout Detection |  |  |  |
| 4 | COMP | Filtering Capacitor | This pin receives a filtering capacitor for power factor correction. Typical values ranges from 1-4.7 μF. |
| 5 | SD | Thermal Foldback and Shutdown | Connecting an NTC to this pin allows the user to program thermal current foldback threshold and slope. A Zener diode can also be used to pull-up the pin and stop the controller for adjustable OVP protection. |
| 6 | CS | Current Sense | This pin monitors the primary peak current. |
| 7 | GND | - | Controller ground pin. |
| 8 | DRV | Driver Output | The driver's output to an external MOSFET |
| 9 | $ V\_{CC} $ | IC Supply Pin | This pin is the positive supply of the IC.The circuit starts to operate when $ V\_{CC} $ exceeds 18 V and turns off when $ V\_{CC} $ goes below 8.8 V (typical values).After start-up,the operating range is 9.4 V up to 26 V ($ V\_{CC}(OVP) $ minimum level). |
| 10 | NC | - | - |

* * *

# NCL30086BH

## INTERNAL CIRCUIT ARCHITECTURE

**Enable VDD VREF** **STOP** **Over Voltage Protection** (Auto−recovery or Latched) **Aux\_SCP OFF** **VCC** **Fault UVLO** **VCC Management** **Management** **Over Temp. Protection Latch** (Auto−recovery or Latched) **Internal** **Thermal VCC\_max VCC Over Voltage** **SD** **Thermal Shutdown Protection** **Foldback V TF WOD\_SCP** **BO\_NOK**

**DRV FF\_mode** **VVS** **VCC** **Zero Crossing Detection Logic FF\_mode** **Aux\_SCP** **ZCD** (ZCD Blanking, Time−Out, ...) **Valley Selection Clamp** **Circuit** **Aux. Winding Short Circuit Prot. Frequency Foldback** **S DRV** **Q** **CS\_ok** **V VS Q**

**Line DIM\_disable R** **feed−forward STOP VVS VREFX**

**GND** **CS Leading Power Factor and** **CS\_reset** **Edge Constant−Current Maximum** **Blanking Control on time** **Ipkmax STOP** **DIM\_disable** **t on,max** **COMP**

**Max. Peak Ipkmax** **Current** **Limit VVS** **BO\_NOK VS** **Brown−Out** **CS\_ok** **CS Short** **Protection** **VREF** **UVLO t on,max** **DIM\_disable** **V DIM** **REFX** **Winding and Dimming** **WOD\_SCP** **Output diode control** **Short Circuit** **Protection** **VTF**

**Figure 3. Internal Circuit Architecture**

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* * *

NCL30086BH

Table 2. MAXIMUM RATINGS TABLE(S)

| Symbol | Rating | Value | Unit |
| --- | --- | --- | --- |
| $V\_{CC}(\\mathrm{MAX})$ | Maximum Power Supply voltage，$V\_{CC}$ pin，continuous voltage | -0.3 to 30 | V |
| $I\_{CC}(\\mathrm{MAX})$ | Maximum current for $V\_{CC}$ pin | Internally limited | mA |
| $V\_{DRV}(\\mathrm{MAX})$ | Maximum driver pin voltage，DRV pin，continuous voltage | -0.3，$V\_{DRV}$ (Note 1) | V |
| $I\_{DRV}(\\mathrm{MAX})$ | Maximum current for DRV pin | -300，+500 | mA |
| $V\_{\\mathrm{MAX}}$ | Maximum voltage on low power pins(except DRV and $V\_{\\mathrm{CC}}$ pins) | -0.3，5.5(Notes2和5) | V |
| $I\_{\\mathrm{MAX}}$ | Current range for low power pins(except DRV and $V\_{\\mathrm{CC}}$ pins) | -2，+5 | mA |
| $R\_{\\theta}\\mathrm{J-A}$ | Thermal Resistance Junction-to-Air | 180 | $^{\\circ}C/W$ |
| $T\_{J}(\\mathrm{MAX})$ | Maximum Junction Temperature | 150 | $^{\\circ}C$ |
|  | Operating Temperature Range | -40 to +125 | $^{\\circ}C$ |
|  | Storage Temperature Range | -60 to +150 | $^{\\circ}C$ |
|  | ESD Capability,HBM model(Note3) | 3.5 | kV |
|  | ESD Capability,MM model(Note3) | 250 | V |
|  | ESD Capability,CDM model(Note3) | 2 | kV |

\\mathrm{V}\_{\\mathrm{C C}}

\\mathrm{V\_{C C}}

\\mathsf{V}\_{\\mathsf{M A X}}

i\_{M A x}

\\mathsf{R}\_{\\mathsf{y J A A}}

^{\\circ}\\mathrm{C}

\\mathsf{T}\_{\\mathsf{J(M(X))}}

^{\\circ}\\mathrm{C}

^{\\circ}\\mathrm{C}

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.

1. VDRV is the DRV clamp voltage VDRV(high) when VCC is higher than VDRV(high). VDRV is VCC otherwise.

should not be assumed, damage may occur and reliability may be affected.

1. VDRV is the DRV clamp voltage VDRV(high) when VCC is higher than VDRV(high). VDRV is VCC otherwise.
2. These levels are low enough not to exceed the maximum ratings of the internal ESD 5.5−V Zener diode. More positive and negative voltages

\\mathrm{V\_{C C}}

\\mathrm{V\_{C C}}

1. VDRV is the DRV clamp voltage VDRV(high) when VCC is higher than VDRV(high). VDRV is VCC otherwise.
2. These levels are low enough not to exceed the maximum ratings of the internal ESD 5.5−V Zener diode. More positive and negative voltages
   can be applied if the pin current stays within the −2 mA / 5 mA range.
3. This device contains ESD protection and exceeds the following tests: Human Body Model 3500 V per JEDEC Standard JESD22−A114E,

can be applied if the pin current stays within the −2 mA / 5 mA range.
3\. This device contains ESD protection and exceeds the following tests: Human Body Model 3500 V per JEDEC Standard JESD22−A114E,
Machine Model Method 250 V per JEDEC Standard JESD22−A115B, Charged Device Model 2000 V per JEDEC Standard JESD22−C101E.
4\. This device contains latch−up protection and has been tested per JEDEC Standard JESD78D, Class I and exceeds ±100 mA.

Machine Model Method 250 V per JEDEC Standard JESD22−A115B, Charged Device Model 2000 V per JEDEC Standard JESD22−C101E.
4\. This device contains latch−up protection and has been tested per JEDEC Standard JESD78D, Class I and exceeds ±100 mA.
5\. Recommended maximum VS voltage for optimal operation is 4 V. −0.3 V to +4.0 V is hence, the VS pin recommended range.

5. Recommended maximum VS voltage for optimal operation is 4 V. −0.3 V to +4.0 V is hence, the VS pin recommended range.

\\mathbf{v\_{s}}

Table 3. ELECTRICAL CHARACTERISTICS (Unless otherwise noted: For typical values TJ = 25°C, VCC = 12 V, VZCD = 0 V,
VCS = 0 V, VSD = 1.5 V) For min/max values TJ = −40°C to +125°C, VCC = 12 V)

T\_{1}=25^{\\circ}C,V C\_{2}=12V\_{1}.C D\_{2}O O V=0\\uparrow

+125^{\\circ}\\mathrm{C}

V\_{C S}=0V\_V{S}D=1.5V)

\\mathsf{T\_{J}}=-4\ {\\dot{0}}^{\\circ}\\mathsf{C}

\| Supply Voltage
Startup Threshold
Minimum Operating Voltage
Hysteresis $V\_{CC(on)}-V\_{CC(off)}$
Internal logic reset \| $V\_{CC}$ rising
$V\_{CC}$ rising
$V\_{CC}$ falling \| $V\_{CC}(on)$
$V\_{CC}(off)$
$V\_{CC}(HYS)$
$V\_{CC}(\\text{reset})$ \| 16.0
8.2
8
4 \| 18.0
8.8
-5 \| 20.0
9.4

-5 \| V \|
\| \-\-\- \| \-\-\- \| \-\-\- \| \-\-\- \| \-\-\- \| \-\-\- \| \-\-\- \|
\| $V\_{CC}$ Over Voltage Protection Threshold \| \| $V\_{CC}(OVP)$ \| 25.5 \| 26.8 \| 28.5 \| V \|
\| $V\_{CC}(off)$ noise filter
$V\_{CC}(\\text{reset})$ noise filter \| \| $t\_{VCC}(off)$
$t\_{VCC}(\\text{reset})$ \| - \| 5
20 \| - \| μs \|
\| Startup current \| \| $I\_{CC}(\\text{start})$ \| - \| 13 \| 30 \| μA \|
\| Startup current in fault mode \| \| $I\_{CC}(\\text{Fault})$ \| \| 58 \| 75 \| μA \|
\| Supply Current
Device Disabled/Fault
Device Enabled/No output load on DRV pin
Device Switching \| $V\_{CC}>V\_{CC}(off)$
$F\_{sw}=65\\text{ kHz}$
$C\_{DRV}=470\\text{ pF}, F\_{sw}=65\\text{ kHz}$ \| $I\_{CC1}$
$I\_{CC2}$
$I\_{CC3}$ \| 0.8

- \| 1.0
  2.6
  3.0 \| 1.2
  4.0
  4.5 \| mA \|

CURRENT SENSE

\\mathsf{V}\_{\\mathrm{l L I M}}

C\_{D R V}=470,p Fup,,F\_{S W}=65,k H

6. Guaranteed by Design
7. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the
   NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after
   an OTP situation.
8. At startup, when VCC reaches VCC(on), the controller blanks OTP for more than 250 s to avoid detecting an OTP fault by allowing the

\\mathsf{F}\_{\\mathsf{s w}}=65;\\mathsf{k H z}

\\mathsf{V c(0V)}

:\\mathsf{R}\_{\\mathsf{T F}\ \\mathsf{s t a n t}}

\\frac{\\mathsf{I C C(s t a r))}}{\\mathsf{{underline{{omathsf{c r}}}}}}

\\mathrm{v}\_{\\mathrm{C C}}

\\operatorname{v}\_{\\mathrm{C C}(\\mathsf{o n})}

an OTP situation.
8\. At startup, when VCC reaches VCC(on), the controller blanks OTP for more than 250 s to avoid detecting an OTP fault by allowing the
SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin.

* * *

NCL30086BH

T\_{J}=25^{\\circ}C,V\_{C C}=12V\_{1}.V\_{2}C D=O V\_{1}

V\_{C S}=0V,V\_{S D}=1.5V,

+125^{\\circ}\\mathrm{C}

\\mathsf{T}{\_\ {mathsf J J}}=-4\\dot{0}{^\\circ}\\mathsf{C}

\\mathsf{V}\_{\\mathsf{C C}}=12,\\mathsf{V})

| Description | Test Condition | Symbol | Min | Typ | Max | Unit |
| --- | --- | --- | --- | --- | --- | --- |
| CURRENT SENSE |  |  |  |  |  |  |
| Propagation delay from current detection to gate off-state |  | tILIM | - | 100 | 150 | ns |
| Maximum on-time |  | ton(MAX) | 26 | 36 | 46 | μs |
| Threshold for immediate fault protection activation |  | VCS(stop) | 1.35 | 1.50 | 1.65 | V |
| Leading Edge Blanking Duration for VCS(stop) |  | tBCS | - | 150 | - | ns |
| Current source for CS to GND short detection |  | ICS(short) | 400 | 500 | 600 | μA |
| Current sense threshold for CS to GND short detection | VCs rising | VCs(low) | 30 | 65 | 100 | mV |

\ \_{\\mathrm{l l l M}}

t{\ }n(M{X})

\\mathsf{V}\_{\\mathsf{C S t o p}}

\\mathsf{V}\_{\\mathsf{C S(o t o p)}}

\ 1mathtt c s s h o t)

1\_{\\mathrm{s N K}}

C\_{\\sf D R V}=470;{\\sf p F}

\ \\mathbf{f}\_{\\mathbf{r}}

C\_{\\sf D R V}=470;{\\sf p F}

\\up\_{\\upup\\up{f}

V\_{\\mathsf D R R}(1w)

\ {sf C C\_{D R V}=470\\tilde{\\sf p F},\\tilde{\\sf R}\_{D R V}=33}

V\_{C C}=V\_{C C(M A X)}

C\_{D R V}=47D F,R D D=33

V\_{\\mathsf D R V(i g h)}

| Upper ZCD threshold voltage | VZCD rising | VZCD(rising) | - | 90 | 150 | mV |
| --- | --- | --- | --- | --- | --- | --- |
| Lower ZCD threshold voltage | VZCD falling | VZCD(falling) | 35 | 55 | - | mV |
| ZCD hysteresis |  | VZCD(HYS) | 15 | - | - | mV |
| Propagation Delay from valley detection to DRV high | VZCD falling | TDEM | - | 100 | 300 | ns |
| Blanking delay after on-time | VREFX>30% VREF | TZCD(blank1) | 1.12 | 1.50 | 1.88 | μs |
| Blanking delay at light load | VREFX<25% VREF | TZCD(blank2) | 0.56 | 0.75 | 0.94 | μs |
| Timeout after last DEMAG transition |  | TTIMO | 5.0 | 6.5 | 8.0 | μs |
| Pulling-down resistor | VZCD=VZCD(falling) | RZCD(PD) | - | 200 | - | kΩ |

V\_{2square D(\\sin g)}

V\_{2C D}(\\tan\\ln)

V\_{2C D}\\sin\\eta

V\_{\\sf C C D D S})

\\mathrm{V}\_{\\mathrm{Z C D}}

{\\mathsf T}\_{\\mathsf D E E},

\\mathrm{V}\_{\\mathrm{Z C D}}

\\mathsf{V} _{\\mathsf{R E F X}}=\\mathsf{V}_{\\mathsf{R E F}}

6. Guaranteed by Design
7. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the

\\mathsf{V}\_{\\mathrm{c o n t r o l}}

\ mathbb\ G{\_{\\mathrm{E A}}}

V\_{R E F X}>30%\ V\_{R E F}

{\\mathsf T}\_{\\mathsf J}=25^{\\circ}{\\mathsf C}

| Reference Voltage at $ T\_{J}=25^{\\circ} \\mathrm{C} $ |  | $ V\_{REF} $ | 245 | 250 | 255 | mV |
| --- | --- | --- | --- | --- | --- | --- |
| Reference Voltage $ T\_{J}=25^{\\circ} \\mathrm{C} $ to 100$^{\\circ} \\mathrm{C}$ |  | $ V\_{REF} $ | 242.5 | 250.0 | 257.5 | mV |
| Reference Voltage $ T\_{J}=-40^{\\circ} \\mathrm{C} $ to 125$^{\\circ} \\mathrm{C}$ |  | $ V\_{REF} $ | 240 | 250 | 260 | mV |
| Current sense lower threshold | $ V\_{CS} $ falling | $ V\_{CS(low)} $ | 20 | 50 | 100 | mV |
| $ V\_{control} $ to current setpoint division ratio |  | $ V\_{ratio} $ | - | 4 | - | - |
| Error amplifier gain | $ V\_{REFX}=V\_{REF} $ | $ G\_{EA} $ | 40 | 50 | 60 | μS |

\\mathsf{T{}\_{J}}=25^{\\circ}\\mathsf{C}

\\mathsf{T}\_{\\mathsf{J}}=-40^{\\circ}\\mathsf{C}

\\frac{12D(b\|a n1)}{2}

\\mathsf{V}\_{\\mathsf{r a t i o}}

\\mathsf{R}\_{0mathsf T(00\\nmid)}

\ {sf I R}\_{T P(\ n)}

\\mathrm{V}{}\_{\\mathrm{C C}}

\\mathsf{V}\_{\\mathrm{C C(o n)}}

* * *

NCL30086BH

T\_{J}=25^{\\circ}C,V\_{C C}=12V\_{1}.V\_{2}C D=O V\_{1}

\\mathsf{T}{\_\ {mathsf J J}}=-4\\dot{0}{^\\circ}\\mathsf{C}

V\_{C S}=0V,V\_{S D}=1.5V,

+125^{\\circ}C,V\_{C C}=12,V)

| Error amplifier current capability | VREFX=VREF(no dimming)VREFX=25%\*VREF | IEA |  | ±60±240 |  | μA |
| --- | --- | --- | --- | --- | --- | --- |
| COMP Pin Start-up Current Source | COMP pin grounded | IEA\_STUP |  | 140 |  | μA |

\\mathsf{V} _{\\mathsf{R E F X}}=\\mathsf{V}_{\\mathsf{R E F}}

V\_{R E F X}=25%\\times V\_{R E F}

LINE FEED FORWARD

| $V\_{VS}$ to $I\_{CS(offset)}$ conversion ratio |  | K\_{LFF}$ | 18 | 20 | 22 | μS |
| --- | --- | --- | --- | --- | --- | --- |
| Line feed-forward current on CS pin | DRV high, $V\_{VS}=2\\text{ V}$ | I\_{FF}$ | 35 | 40 | 45 | μA |
| Offset current maximum value |  | I\_{offset(MAX)}$ | 80 | 100 | 120 | μA |

\\mathsf{K}\_{\\mathsf{L F F}}

\\mathrm{V}\_{\\mathrm{V S}}

\ 1\ !\\mathsf{C s(o f s e e)}

V\_{V S}=2V

\ \_\\mathsf{F}

\\upmu A

\\mathrm{v}\_{\\mathrm{V S}}

| Threshold for high-line range(HL) detection | $V\_{VS}$ rising | $V\_{HL}$ | 2.28 | 2.40 | 2.52 | V |
| --- | --- | --- | --- | --- | --- | --- |
| Threshold for low-line range(LL) detection | $V\_{VS}$ falling | $V\_{LL}$ | 2.18 | 2.30 | 2.42 | V |
| Blanking time for line range detection |  | tHL(blank) | 15 | 25 | 35 | ms |

\\mathsf{V}{}\_{\\mathsf{H L}}

\\mathrm{V}\_{\\mathrm{V S}}

\\mathrm{V\_{L L}}

t\_{H L(b\|a n k)}

FREQUENCY FOLDBACK

| Minimum additional dead time in frequency fold-back mode |  | tFF1LL | 1.4 | 2.0 | 2.6 | μs |
| --- | --- | --- | --- | --- | --- | --- |
| Additional dead time | VREFX=5% VREF | tFF2HL | - | 40 | - | μs |
| Additional dead time | VREFX=0% VREF | tFF3HL | 90 |  | - | μs |

\ \_F F1L L

V\_{R E F X}=5%\_{R E F}

Vmathsf{E F X}=0%\\vee\_E E F

FAULT PROTECTION

| Thermal Shutdown(Note 6) | $F\_{SW}=65\\text{ kHz}$ | $T\_{SHDN}$ | 130 | 150 | 170 | $^\\circ\\text{C}$ |
| --- | --- | --- | --- | --- | --- | --- |
| Thermal Shutdown Hysteresis |  | $T\_{SHDN}(HYS)$ | - | 50 | - | $^\\circ\\text{C}$ |
| Threshold voltage for output short circuit or aux. winding short circuit detection |  | $V\_{ZCD}(\\text{short})$ | 0.8 | 1.0 | 1.2 | V |
| Short circuit detection Timer | $V\_{ZCD}< V\_{ZCD}(\\text{short})$ | $t\_{OVLD}$ | 70 | 90 | 110 | ms |
| Auto-recovery timer duration |  | $t\_{\\text{recovery}}$ | 3 | 4 | 5 | s |
| SD pin Clamp series resistor |  | $R\_{SD}(\\text{clamp})$ |  | 1.6 |  | k$\\Omega$ |
| Clamped voltage | SD pin open | $V\_{SD}(\\text{clamp})$ | 1.13 | 1.35 | 1.57 | V |
| SD pin detection level for OVP | $V\_{SD}\\text{ rising}$ | $V\_{OVP}$ | 2.35 | 2.50 | 2.65 | V |
| Delay before OVP or OTP confirmation |  | $T\_{SD}(\\text{delay})$ | 22.5 | 30.0 | 37.5 | $\\mu s$ |
| Reference current for direct connection of an NTC (Note 8) |  | $I\_{OTP}(\\text{REF})$ | 80 | 85 | 90 | $\\mu A$ |
| Fault detection level for OTP (Note 7) | $V\_{SD}\\text{ falling}$ | $V\_{OTP}(\\text{off})$ | 0.47 | 0.50 | 0.53 | V |
| SD pin level for operation recovery after an OTP detection | $V\_{SD}\\text{ rising}$ | $V\_{OTP}(\\text{on})$ | 0.66 | 0.70 | 0.74 | V |
| OTP blanking time when circuit starts operating (Note 8) |  | $t\_{OTP}(\\text{start})$ | 250 |  | 370 | $\\mu s$ |
| SD pin voltage where thermal fold-back starts ($V\_{REF}$ is decreased) |  | $V\_{TF}(\\text{start})$ | 0.94 | 1.00 | 1.06 | V |
| SD pin voltage at which thermal fold-back stops ($V\_{REF}$ is clamped to $V\_{REF50}$) |  | $V\_{TF}(\\text{stop})$ | 0.64 | 0.69 | 0.74 | V |
| $V\_{TF}(\\text{start})$ over $I\_{OTP}(\\text{REF})$ ratio (Note 7) | $T\_{J}=+25^{\\circ}\\mathrm{C}$ to $+125^{\\circ}\\mathrm{C}$ | $R\_{TF}(\\text{start})$ | 10.8 | 11.7 | 12.6 | k$\\Omega$ |

\\mathsf{F}\_{\\mathsf{S W}}=65,\\mathsf{K H z}

^{\\circ}\\mathrm{C}

\\mathsf{T}\_{\\mathsf S H H N(mathsf H\ {S S})}

^{\\circ}\\mathrm{C}

V\_{\ {C}D(\ s\ {slash07}}

T{J\ }=+25^{\\circ}C\\tan10+125^{\\circ}C

6. Guaranteed by Design

7. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the

8. Guaranteed by Design

9. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the
   NTC must exhibit to respectively, enter thermal foldback, stop thermal foldback, trigger the OTP limit and allow the circuit recovery after
   an OTP situation.

10. At startup, when VCC reaches VCC(on), the controller blanks OTP for more than 250 s to avoid detecting an OTP fault by allowing the

\\mathsf{R}\_{\\mathsf{T F(s t a n t)}},

\\mathsf{R}\_{\\mathsf{T T F s t a n t}}

\\underline{{\\mathsf{T}\_{\ {S D(d e l a y)}}}}

\\mathsf{R\_{T P(o f f)}}

\\mathsf{R}\_{0mathsf T(o n)}

\\mathsf{V}\_{0mathsf T(o nmathsf{{n}})}

\ \_\\mathsf{O O P(s t a n t)}

\\mathsf{V}\_{\\mathrm{C C}n}(\\mathsf{o n})

* * *

NCL30086BH

T\_{J}=25^{\\circ}C,V\_{C C}=12V\_{1}.V\_{2}C D=O V\_{1}

\\mathsf{T}{\_\ {mathsf J J}}=-4\\dot{0}{^\\circ}\\mathsf{C}

V\_{C S}=0V,V\_{S D}=1.5V,

+125^{\\circ}C,V\_{C C}=12V)

| Description | Test Condition | Symbol | Min | Typ | Max | Unit |
| --- | --- | --- | --- | --- | --- | --- |
| FAULT PROTECTION |  |  |  |  |  |  |
| $V\_{TF(stop)}$ over $I\_{OTP(REF)}$ ratio (Note 7) | $T\_{J}=+25^{\\circ}C$ to $+125^{\\circ}C$ | $R\_{TF(stop)}$ | 7.4 | 8.1 | 8.8 | k$\\Omega$ |
| $V\_{OTP(off)}$ over $I\_{OTP(REF)}$ ratio (Note 7) | $T\_{J}=+25^{\\circ}C$ to $+125^{\\circ}C$ | $R\_{OTP(off)}$ | 5.4 | 5.9 | 6.4 | k$\\Omega$ |
| $V\_{OTP(on)}$ over $I\_{OTP(REF)}$ ratio (Note 7) | $T\_{J}=+25^{\\circ}C$ to $+125^{\\circ}C$ | $R\_{OTP(on)}$ | 7.5 | 8.1 | 8.7 | k$\\Omega$ |
| $V\_{REFX}$ @ $V\_{SD}=600mV$ (as percentage of $V\_{REF}$) | SD pin falling (no OTP detection) | $V\_{REF}(50)$ | 40 | 50 | 60 | % |

\\mathsf{V} _{\\mathsf{T F({s t o p})}},{\\mathsf{o v e r}},\|_{\\mathsf{O T P({R E F})}}

\ \_\ mathsf J+225^{\\circ}C\\tan1+125^{\\circ}C

\\mathsf{R}\_{\\mathsf{T F(s t o p)}}

T\_{J}=+25^{\\circ}C1tan0+125^{\\circ}C

\\mathsf{R}\_{\\mathsf T T Pmathsf\\\mathsf left(f f\\right}}

\ \_\ mathsf J+225^{\\circ}C\\,10+125^{\\circ}C

\\mathsf{R}\_{0mathsf T(o n)}

\\mathsf{V}\_{\\mathsf{R E F}})

| Brown-Out ON level(IC start pulsing) | V$\_{S}$ rising | V$\_{BO(on)}$ | 0.95 | 1.00 | 1.05 | V |
| --- | --- | --- | --- | --- | --- | --- |
| Brown-Out OFF level(IC shuts down) | V$\_{S}$ falling | V$\_{BO(off)}$ | 0.85 | 0.90 | 0.95 | V |
| BO comparators delay |  | t$\_{BO(delay)}$ |  | 30 |  | μs |
| Brown-Out blanking time |  | t$\_{BO(blank)}$ | 15 | 25 | 35 | ms |
| V$\_{S}$ pin Pulling-down Current | V$ _{S}=V_{BO(on)}$ | I$\_{BO(bias)}$ | 50 | 250 | 450 | nA |

\\mathsf{V}\_{\\mathsf B O(\\mathsf O f))}}

\\mathsf{t}{\\mathsf{B O}}(\\mathsf{d e a y})

\ {{\\sf t}}\_{\\tt B B O}a l a n k)

V\_{S}=V\_{B O(o n)}

\ \_{\\mathsf B0(\\mathsf b i a s)}

DIMMING SECTION

\\mathsf{V}\_{\\mathsf{D I M}},\\mathsf{f a l l i n g}

\\mathsf{V}\_{\\mathsf{D M O}}

| DIM pin voltage for zero output current(OFF voltage) | VDIM falling | VDIM0 | 0.66 | 0.70 | 0.74 | V |
| --- | --- | --- | --- | --- | --- | --- |
| DIM pin voltage for maximum output current(VREF-FX=VREF) | VDIM rising | VDIM100 | - | 2.45 | 2.60 | V |
| DIM pin voltage for 50% output current(VREFFX=125mV) | VDIM rising or falling | VDIM50 | 1.35 | 1.57 | 1.75 | V |
| Dimming range |  | VDIM(range) |  | 1.75 |  | V |
| Dimming pin pull-up current source |  | IDIM(pullup) | 7.5 | 9.6 | 12 | μA |

\\mathsf{V}\_{\\mathsf D M M100}

\\mathsf{V}\_{\\mathsf{D M}}

F X=V\_{\\sf R E F})

\\mathsf{V}\_{\\mathsf{D l M}}

\\mathsf{V}\_{\\mathsf{D M500}}

(mathsf V{\_{R E F X}}=125\ m)

V\_{\\sf{D M(r a n g e)}}

6. Guaranteed by Design

7. A NTC is generally placed between the SD and GND pins. Parameters RTF(start), RTF(stop), ROTP(off) and ROTP(on) give the resistance the

8. Guaranteed by Design

10. At startup, when VCC reaches VCC(on), the controller blanks OTP for more than 250 s to avoid detecting an OTP fault by allowing the

\\mathsf{R}\_{0mathsf T(o nmathsf{)n}}

\\mathsf{V}\_{\\mathrm{C C(o n)}}

250,\\upmu\\mathrm{s}

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.

* * *

NCL30086BH

TYPICAL CHARACTERISTICS

TJ, JUNCTION TEMPERATURE (°C)

Figure 4. VCC Start−up Threshold vs.
Temperature

\\mathbf{v}\_{\\mathbf{c c}}

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. VCC Minimum Operating Voltage vs.
Temperature

V\_{C C(o n)}-V\_{C(O f)}\\cup

Figure 6. Hysteresis (VCC(on)− VCC(off)) vs.
Temperature

Figure 7. VCC(reset) vs. Temperature

* * *

NCL30086BH

TYPICAL CHARACTERISTICS

TJ, JUNCTION TEMPERATURE (°C)

Figure 8. VCC Over Voltage Protection
Threshold vs. Temperature

TJ, JUNCTION TEMPERATURE (°C)

TJ, JUNCTION TEMPERATURE (°C)

Figure 9. Start−up Current vs. Temperature

(^{\\circ}!{\\bf C})

Figure 10. Start−up Current in Fault Mode vs.
Temperature

Figure 12. ICC2 vs. Temperature

\\top\_{\\mathbf{J}}

\ \_{\\mathbf{c c2}}

Figure 11. ICC1 vs. Temperature

TJ, JUNCTION TEMPERATURE (°C)

* * *

NCL30086BH

TYPICAL CHARACTERISTICS

TJ, JUNCTION TEMPERATURE (°C)

Figure 14. Maximum Internal Current Limit vs.
Temperature

TJ, JUNCTION TEMPERATURE (°C)

TJ, JUNCTION TEMPERATURE (°C)

Figure 18. VCS(stop) vs. Temperature

\\top\_{\\mathbf{J}}

Figure 15. Leading Edge Blanking vs.
Temperature

Figure 16. Current Limit Propagation Delay vs.
Temperature

TJ, JUNCTION TEMPERATURE (°C)

Figure 19. Leading Edge Blanking Duration for
VCS(stop) vs. Temperature

* * *

NCL30086BH

TYPICAL CHARACTERISTICS

TJ, JUNCTION TEMPERATURE (°C)

Figure 20. ICS(short) vs. Temperature

TJ, JUNCTION TEMPERATURE (°C)

Figure 21. VCS(low), VCS Rising vs.
Temperature

Figure 24. Gate Drive Rise Time vs.
Temperature

Figure 22. Sink Gate Drive Resistance vs.
Temperature

TJ, JUNCTION TEMPERATURE (°C)

Figure 25. Gate Drive Fall Time
(CDRV = 470 pF) vs. Temperature

* * *

NCL30086BH

TYPICAL CHARACTERISTICS

TJ, JUNCTION TEMPERATURE (°C)

Figure 26. DRV Low Voltage vs. Temperature

TJ, JUNCTION TEMPERATURE (°C)

Figure 27. DRV High Voltage vs. Temperature

Figure 28. Upper ZCD Threshold Voltage vs.
Temperature

Figure 30. ZCD Hysteresis vs. Temperature

TJ, JUNCTION TEMPERATURE (°C)

Figure 31. ZCD Blanking Delay vs.
Temperature

* * *

NCL30086BH

TYPICAL CHARACTERISTICS

TJ, JUNCTION TEMPERATURE (°C)

Figure 32. ZCD Time−out vs. Temperature

TJ, JUNCTION TEMPERATURE (°C)

Figure 33. Reference Voltage vs. Temperature

(^{\\circ}!{\\bf C})

Figure 36. Feedforward VVS to ICS(offset)
Conversion Ratio vs. Temperature

Figure 34. Current Sense Lower Threshold
(VCS Falling) vs. Temperature

\\top\_{\\mathbf{J}}

\\mathbf{v}\_{\\mathbf{v s}}

Figure 35. Error Amplifier Trans−conductance
Gain vs. Temperature

Figure 37. Line Feedforward Current on CS
Pin (@ VVS = 2 V) vs. Temperature

V\_{V S}=2V

* * *

NCL30086BH

TYPICAL CHARACTERISTICS

TJ, JUNCTION TEMPERATURE (°C)

Figure 38. Ioffset(MAX) vs. Temperature

TJ, JUNCTION TEMPERATURE (°C)

Figure 39. Threshold for High−line Range
Detection vs. Temperature

Figure 40. Threshold for Low−line Range
Detection vs. Temperature

Figure 42. Threshold Voltage for Output Short
Circuit Detection vs. Temperature

TJ, JUNCTION TEMPERATURE (°C)

Figure 43. Short Circuit Detection Timer vs.
Temperature

\ \\boldsymbol{\\mathsf{T}}\_{\\mathbf{J}}

* * *

NCL30086BH

TYPICAL CHARACTERISTICS

TJ, JUNCTION TEMPERATURE (°C)

Figure 44. Auto−recovery Timer Duration vs.
Temperature

TJ, JUNCTION TEMPERATURE (°C)

Figure 48. TSD(delay) vs. Temperature

Figure 46. SD Pin Clamp Voltage vs.
Temperature

Figure 45. SD Pin Clamp Series Resistor vs.
Temperature

TJ, JUNCTION TEMPERATURE (°C)

Figure 47. SD Pin OVP Threshold Voltage vs.
Temperature

\ \\boldsymbol{\\mathsf{T}}\_{\\mathbf{J}}

* * *

NCL30086BH

TYPICAL CHARACTERISTICS

TJ, JUNCTION TEMPERATURE (°C)

Figure 50. RTF(start) vs. Temperature

TJ, JUNCTION TEMPERATURE (°C)

Figure 51. RTF(stop) vs. Temperature

Figure 52. ROTP(off) vs. Temperature

Figure 54. Ratio VREF(50) over VREF vs.
Temperature

Figure 53. ROTP(on) vs. Temperature

Figure 55. Brown−out ON Level vs.
Temperature

* * *

NCL30086BH

TYPICAL CHARACTERISTICS

Figure 56. Brown−out OFF Level vs.
Temperature

Figure 57. Brown−out Blanking Time vs.
Temperature

Figure 58. VS Pin Pulling−down Current vs.
Temperature

* * *

NCL30086BH

APPLICATION INFORMATION

The NCL30086BH is a driver for power−factor corrected
flyback and non−isolated buck−boost/ SEPIC converters. It
implements a current−mode, quasi−resonant architecture
including valley lockout and frequency fold−back
capabilities for maintaining high−efficiency performance
over a wide load range. A proprietary circuitry ensures both
accurate regulation of the output current (without the need
for a secondary−side feedback) and near−unity power factor
correction. The circuit contains a suite of powerful
protections to ensure a robust LED driver design without the
need of extra external components or overdesign
• Quasi−Resonance Current−Mode Operation:

• Quasi−Resonance Current−Mode Operation:
implementing quasi−resonance operation in peak
current−mode control, the NCL30086BH optimizes the
efficiency by turning on the MOSFET when its
drain−source voltage is minimal (valley). In light−load
conditions, the circuit changes valleys to reduce the
switching losses. For a stable operation, the valley at
which the MOSFET switches on remains locked until
the input voltage or the output current set−point
significantly changes.
• Primary−Side Constant−Current Control with

• Primary−Side Constant−Current Control with
Power Factor Correction: a proprietary circuitry
allows the LED driver to achieve both near−unity
power factor correction and accurate regulation of the
output current without requiring any secondary−side
feedback (no optocoupler needed). A power factor as
high as 0.99 and an output current deviation below ±2%
are typically obtained.
• Linear or PWM dimming: the DIM pin allows

• Linear or PWM dimming: the DIM pin allows
implementing both analog and PWM dimming.
• Main protection features:

¨ Over Temperature Thermal Fold−back/
Shutdown/Over Voltage Protection: the
NCL30086BH features a gradual current foldback to
protect the driver from excessive temperature down
to 50% of the programmed current. If the
temperature continues to rise after this point to a
second level, the controller stops operating. This
mode would only be expected to be reached under
normal conditions if there is a severe fault. The first

and second temperature thresholds depend on the
NTC connected to the circuit SD pin. The SD pin
can also be used to shutdown the device by pulling
this pin below the VOTP(off) min level. A Zener
diode can also be used to pull−up the pin and stop
the controller for adjustable OVP protection. When
triggered, both protections lead the controller to stop
operating for the 4−s auto−recovery time.
¨ Cycle−by−cycle peak current limit: when the

\\mathrm{V\_{0T P(f f)}}

¨ Cycle−by−cycle peak current limit: when the
current sense voltage exceeds the internal threshold
VILIM, the MOSFET is immediately turned off.
¨ Winding or Output Diode Short−Circuit

¨ Winding or Output Diode Short−Circuit
Protection: an additional comparator senses the CS
signal and stops the controller for the 4−s
auto−recovery time if it exceeds 150% x VILIM for
4 consecutive cycles. This feature can protect the
converter if a winding is shorted or if the output
diode is shorted or simply if the transformer
saturates.
Output Short−circuit protection: if the ZCD pin

¨ Output Short−circuit protection: if the ZCD pin
voltage remains low for a 90−ms time interval, the
controller detects that the output or the ZCD pin is
grounded and hence, stops operation for the 4−s
auto−recovery time.
¨ Open LED protection: if the VCC pin voltage

¨ Open LED protection: if the VCC pin voltage
exceeds the OVP threshold, the controller shuts
down and waits 4 seconds before restarting
switching operation.
¨ Floating or Short Pin Detection: NCL30086BH

¨ Floating or Short Pin Detection: NCL30086BH
protections aid in pass safety tests. For instance, the
circuit stops operating when the CS pin is grounded
or open.

Figure 59. Power Factor and Constant−Current Control

Power Factor and Constant Current Control
The NCL30086BH embeds an analog/digital block to

Power Factor and Constant Current Control
The NCL30086BH embeds an analog/digital block to
control the power factor and regulate the output current by
monitoring the ZCD, VS and CS pin voltages (signals ZCD,
VS and VCS of Figure 59). This circuitry generates the
current setpoint (VCONTROL/4) and compares it to the
current sense signal (VCS) to dictate the MOSFET turning
off event when VCS exceeds VCONTROL/4.

* * *

NCL30086BH

The VS pin provides the sinusoidal reference necessary
for shaping the input current. The obtained current reference
is further modulated so that when averaged over a half−line
period, it is equal to the output current reference (VREFX).
This averaging process is made by an internal Operational
Trans−conductance Amplifier (OTA) and the capacitor
connected to the COMP pin (C1 in Figure 59). Typical
COMP capacitance is 2.2 F and should not be less than 1 F
to ensure stability. The COMP ripple does not affect the
power factor performance as the circuit digitally eliminates
it when generating the current setpoint.
If the VS pin properly conveys the sinusoidal shape, power

<1

2.2,\\upmu\\mathrm{F}

1,\\up\\mu F

If the VS pin properly conveys the sinusoidal shape, power
factor will be close to 1. Also, the Total Harmonic Distortion
(THD) will be low, especially if the output voltage ripple is
small. In any case, the output current will be well regulated
following the equation below:
V

\\mathbf{V}\_{\\mathrm{S}}

\\mathsf{I} _{\\mathsf{o u t}}=\\frac{\\mathsf{V}_{\\mathsf{R E F X}}}{2\\mathsf{N}\_{\\mathsf{P S}}\\mathsf{R}s e n s e}

Where:
• N

• NPS is the secondary to primary transformer turns NPS
= NS / NP
• R is the current sense resistor (see Figure 1).

\\mathrm{N p s}

• Rsense is the current sense resistor (see Figure 1).
• V is the output current internal reference. VREFX =

\\mathrm{R\_{s e n s e}}

• VREFX is the output current internal reference. VREFX =
VREF (250 mV, typically) at full load.

\\mathrm{V\_{R E F X}}

\\mathrm{V}{}\_{\\mathrm{R E F}}

\\mathrm{(V\_{R E F X})}

\\mathrm{V}{}mathrm{R E F}

If a major fault is detected, the circuit enters the
latched−off or auto−recovery mode and the COMP pin is
grounded (except in an UVLO condition). This ensures a
clean start−up when the circuit resumes operation.

\\mathrm{V}{}\_{\\mathrm{D I M}00}

Generally an LED lamp is expected to emit light in < 1 sec
and typically within 300 ms. The start−up phase consists of
the time to charge the VCC capacitor, initiate startup and
begin switching and the time to charge the output capacitor
until sufficient current flows into the LED string. To
speed−up this phase, the following defines the start−up
sequence:
• The COMP pin is grounded when the circuit is off. The

Start−up Sequence
Generally an LED lamp is expected to emit light in < 1 sec

\\mathbf{V}\_{\\mathrm{C C}}

• The COMP pin is grounded when the circuit is off. The
average COMP voltage needs to exceed the VS pin
peak value to have the LED current properly regulated
(whatever the current target is). To speed−up the COMP
capacitance charge and shorten the start−up phase, an
internal 80− A current source adds to the OTA sourced
current (60 A max typically) to charge up the COMP
capacitance. The 80− A current source remains on until
the OTA starts to sink current as a result of the COMP
pin voltage sufficient rise. At that moment, the COMP
pin being near its steady−state value, it is only driven
by the OTA.
• If V drops below the V threshold because the

80{-mumu}}}

(60,\\upmu\\mathrm{a}}

80{-}{\\upmu}\\mathbf{A}

\\mathrm{V\_{C C}}

• If VCC drops below the VCC(off) threshold because the
circuit fails to start−up properly on the first attempt, a
new attempt takes place as soon as VCC is recharged to
VCC(on). The COMP voltage is not reset at that
moment. Instead, the new attempt starts with the
COMP level obtained at the end of the previous
operating phase.
• If the load is shorted, the circuit will operate in hiccup

\\mathrm{V C(o f f)}

\\mathrm{V}{}\_{\\mathrm{C C(o n}}

• If the load is shorted, the circuit will operate in hiccup
mode with VCC oscillating between VCC(off) and
VCC(on) until the AUX\_SCP protection trips
(AUX\_SCP is triggered if the ZCD pin voltage does
not exceed 1 V within a 90−ms operation period of time
thus indicating a short to ground of the ZCD pin or an
excessive load preventing the output voltage from
rising). The AUX\_SCP protection forces the 4−s
auto−recovery delay to reduce the operation duty−ratio.
Figure 60 illustrates a start−up sequence with the output
shorted to ground.

\\mathrm{V\_{C C(o n)}}

^{4-mathrm s}

* * *

NCL30086BH

Figure 60. Start−up Sequence in a Load Short−circuit Situation

Zero Crossing Detection Block
The ZCD pin detects when the drain−source voltage of the

The ZCD pin detects when the drain−source voltage of the
power MOSFET reaches a valley by crossing below the
55−mV internal threshold (VZCD(TH)). At startup or in case
of extremely damped free oscillations, the ZCD comparator
may not be able to detect the valleys. To avoid such a

\\mathrm{(V\_{Z C D(T H)})}

situation, the NCL30086BH features a time−out circuit that
generates pulses if the voltage on ZCD pin stays below the
55−mV threshold for 6.5 s nominal. The time−out also acts
as a substitute clock for the valley detection and simulates
a missing valley in case the free oscillations are too damped.

* * *

NCL30086BH

Figure 61. Zero Current Detection Block

* * *

# NCL30086BH

If the ZCD pin or the auxiliary winding happen to be shorted, the time−out function would normally make the controller keep switching and hence lead to improper LED current value. The “AUX\_SCP” protection prevents such a stressful operation: a secondary timer starts counting that is only reset when the ZCD voltage exceeds the VZCD(short) threshold (1 V typically). If this timer reaches 90 ms (no ZCD voltage pulse having exceeded VZCD(short) for this time period), the controller detects a fault and stops operation for 4 seconds. The “clock” shown in Figure 61 is used by the “valley selection frequency foldback” circuitry of the block diagram (Figure 3), to generate the next DRV pulse (if no fault prevents it):

- Immediately when the clock occurs in QR mode at low line or valley 2 at high line (full load)
- After the appropriate number of “clock” pulses in thermal foldback or dimming mode **For an optimal operation, the maximum ZCD level** **should be maintained below 5 V to stay safely below the** **built in clamping voltage of the pin.** **Line Range Detection** As sketched in Figure 62, this circuit detects the low−line range if the VS pin remains below the VLL threshold (2.3 V typical) for more than the 25−ms blanking time. High−line is detected as soon as the VS pin voltage exceeds VHL (2.4 V typical). These levels roughly correspond to 184−V rms and 192−V rms line voltages if the external resistors divider applied to the VS pin is designed to provide a 1−V peak value at 80 V rms.
  In the low−line range, conduction losses are generally dominant. Adding a dead−time would further increase these losses. Hence, only a short dead−time is necessary to reach the MOSFET valley. In high−line conditions, switching losses generally are the most critical. It is thus efficient to skip one valley to lower the switching frequency. Hence, under normal operation, the NCL30086BH optimizes the

**(right)**

**Line Feedforward** To compensate for current regulation errors due to AC line variation, the NCL30086BH includes a method to add line feedforward adjustment. As illustrated by Figure 64, the input voltage is sensed by the VS pin and converted into a

efficiency over the line range by turning on the MOSFET at the first valley in low−line conditions and at the second valley in the high−line case. This is illustrated by Figure 63 that sketches the MOSFET Drain−Source voltage in both cases. In the event that thermal foldback is activated, additional valleys can be skipped as the power is reduced.

current. By adding an external resistor in series between the sense resistor and the CS pin, a voltage offset proportional to the input voltage is added to the CS signal for the MOSFET on−time.

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**Figure 62. Line Range Detection**

**Figure 63. Full−load Operation − Quasi−resonant Mode in low line (left), turn on at valley 2 when in high line**

**[www.onsemi.com](/content/site-root.html)**

* * *

NCL30086BH

Figure 64. Line Feed−Forward Schematic

In Figure 64, Q\_drv designates the output of the PWM latch which is high for the on−time and low otherwise.

PWM or Linear Dimming Detection
The DIM pin of the NCL30086BH is provided to

The DIM pin of the NCL30086BH is provided to
implement linear and/or PWM dimming of the LED current.
Applying a voltage on the DIM pin voltage (VDIM) forces

Applying a voltage on the DIM pin voltage (VDIM) forces
the output current internal reference to operate in one of
three regions:

\ \ (\\mathrm{V}\_{\\mathrm{D I M}})

\\mathsf{V} _{\\mathsf{R E F X}}=0\\qquad\\qquad\\qquad\\mathsf{i f}\ mathsf{V}_\\mathsf{{D M M}}\\leq\\mathsf{V}\_{\\mathsf{D M M0}}

\\begin array}{r}{\\mathsf{V} _{\\mathsf{R E F X}}=\\mathsf{V}_{\\mathsf{R E F}}\\qquad\\qquad\\qquad\\mathrm{i f~}\\mathsf{V} _{\\mathsf{D I M}}\\geq\\mathsf{V}_{\\mathsf{D I M100}}}\\end{array}

\\mathsf{V} _{\\mathsf{R E F X}}=\\frac{\\mathsf{V}_{\\mathsf{D I M}}-\\mathsf{V} _{\\mathsf{D I M0}}}{\\mathsf{V}_{\\mathsf{D I M100}}-\\mathsf{V} _{\\mathsf{D I M0}}}\\mathsf{V}_{\\mathsf{R E F}}\\qquad\\mathsf{o t h e r w i s e}

VDIM0 and VDIM100 respectively, are 0.7 V and 2.45 V
typically.
The output current can then be controlled by the DIM pin

\\mathrm{V}{}\_{\\mathrm{D I M0}}

\\mathrm{V\_{D I M100}}

The output current can then be controlled by the DIM pin
as follows:

\\begin{array}{r l}&{\\mathsf{I} _{\\sf o u t}=\\mathsf{0}}\ &{\\mathsf{I}_{\\sf o u t}=\\mathsf{I} _{\\sf o u t,n o m}=\\frac{\\mathsf{V}_{\\sf R E F}}{2\\mathsf{N} _{\\sf P S}\\mathsf{R}_{\\sf s e n s e}};;\\mathsf{i f}\ \\mathsf{V} _{\\sf D M M}\\geq\\mathsf{V}_{\\sf D M M00}}\\end&array}

(eq. 3)

Where:
• N

• NPS is the secondary to primary transformer turns
N N N
PS S P
• R

\\mathsf{I}{ _{o u t}}=\\frac{\\mathsf{V}_{\\mathsf{D I M}}-\\mathsf{V} _{\\mathsf{D I M0}}}{\\mathsf{V}_{\\mathsf{D I M100}}-\\mathsf{V} _{\\mathsf{D I M0}}}\\mathsf{I}{_{o u t,n o m}}\ \ \\\ \\\ mathsf o t t e r w i s e

\\sf N\_{P S}=N\_{S}/N\_{P}

• VREF is the output current internal reference (250 mV
typically)
• I is the full−load output current.

• Rsense is the current sense resistor (see Figure 1).
• V is the output current internal reference (250 mV

\\mathrm{R\_{s e n s e}}

• Iout,nom is the full−load output current.
The DRV output is disabled whenever the DIM pin

The DRV output is disabled whenever the DIM pin
voltage is lower than VDIM0 and the output current setpoint
is maximal when VDIM exceeds VDIM100. Thus, for PWM
dimming, a PWM signal with a low−state value below
VDIM0 and a high−state value above VDIM100 should be
applied.

\\mathrm{V}{}\_{\\mathrm{R E F}}

Figure 65. Pin DIM Chronograms

\\mathrm{V}{}\_{\\mathrm{D I M0}}

\\mathrm{V}{}\_{\\mathrm{D I M}00}.

\\mathrm{V\_{D I M0}}

In this case, the output current will be:

(eq. 4)

\\mathsf{I{ _{o u t}\ }cong I_{o u t,n o m}\\cdot\\mathsf{d}}

V\_{D I M O}^{\\phantom{-}}=cdots{-}.

Where d is the duty ratio of the DIM pin signal.

* * *

NCL30086BH

Notes:
• The current does not immediately reach its new target

• The current does not immediately reach its new target
value when the PWM dimming signal state changes due
to system time constants like the time necessary to
charge or discharge the output capacitor to the required
level. The output current settling time can hence affect
the obtained output current, particularly if the PWM
signal frequency is high.

• If either the high−state (VDIM(high)) or low−state level
(VDIM(low)) of the input or both are between VDIM0 and
VDIM100, the output current will be proportionally
reduced as both analog and PWM dimming are
simultaneous active, thus the output current will be:

\\sf{I} _{o u t}\\equiv\\left(\\frac{V_{O u(b0p p)}-V\_{O u b}}{V\_{O u(b0p0)}-V\_{O u b0}}\ {sf{}}{\\sf{d}}+\\frac{V\_{O u b(p0p)}-V\_{O u b0}}{V\_{O u(b1p0)}-V\_{O u b0}}(1-4)\\right)sf I I\_{o u t,s o m}\ f\ V\_{O u b0}\\le V\_{O u b(0p o)}\ V\_{O u b(p0p)}\\le\ sf V V\_{O u b(0p00}

\\sf{I f}\ V\_{D I M0},\\equiv,V\_{D I M(n i g g h)},\\equiv,V\_{D I M O0},,{a n d},,V\_{D I M(l o o w)},\\equiv,\\vee V\_{D I M0}

\\sf{I} _{o u t}\\cong\\left({sf{d}}+\\frac{V_{D M M(o w w)}-V\_{D M M0}}{V\_{D M M10}-V\_{D M M0}}(1,-,{\\sf{d}})\\right)\\sf{I}\_{o u t,n o m}

\\mathsf{f f}\ mathsf V{{\\sfsf\_}{{\\sf M M}{\\sf(}i{\\sf}g9)}}\\geq\\mathsf{V} _{{\\sf D}}{\\sf M}{100}\ \\mathsf{a n d}\ \\mathsf{V}_{{\\sf D}}{\\sf V} _{{\\sf D\ }{\\sf D}{\\sf M}0}\\leq\\mathsf{V}_{{\\sf D\ }{\\sf D}{\\sf(sf}000)}\\leq\\mathsf{V}\_{{\\sf D}{\\sf M\ }100}

• If thermal foldback is activated as well, the current
reduction is cumulative. For instance, if the DIM pin
voltage and the thermal foldback respectively, reduces
the output current setpoint by 50% and 20%
respectively, the output current will be 80%\*50% that is
40% of its nominal level.
The DIM pin is pulled up internally by a 10− A current source.

The DIM pin is pulled up internally by a 10− A current source.
Thus, if the pin is let open, the controller is able to start.
For any power factor corrected single stage architecture

Thus, if the pin is let open, the controller is able to start.
For any power factor corrected single stage architecture
there will be a component of line ripple (100 / 120 Hz) on the
output. If PWM dimming is used, it is recommended to
select the dimming frequency to be sufficiently high not to
generating beat frequencies that could create optical
artifacts.

> > As a general rule, the minimum PWM frequency

> > As a general rule, the minimum PWM frequency
> > should be at least 2.5x the line ripple frequency and not
> > be set near multiples of the line frequency.

The circuit incorporates a full suite of protection features
listed below to make the LED driver very rugged.

PROTECTIONS
The circuit incorporates a full suite of protection features

Output Short Circuit Situation
An overload fault is detected if the ZCD pin voltage

An overload fault is detected if the ZCD pin voltage
remains below VZCD(short) for 90 ms. In such a situation, the
circuit stops generating pulses until the 4−s delay
auto−recovery time has elapsed.

Winding or Output Diode Short Circuit Protection
If a transformer winding happens to be shorted, the

Winding or Output Diode Short Circuit Protection
If a transformer winding happens to be shorted, the
primary inductance will collapse leading the current to ramp
up in a very abrupt manner. The VILIM comparator (current
limitation threshold) will trip to open the MOSFET and
eventually stop the current rise. However, because of the
abnormally steep slope of the current, internal propagation
delays and the MOSFET turn−off time, a current rise > 50%
of the nominal maximum value set by VILIM is possible. As
illustrated in Figure 66, an additional circuit monitors for
this current overshoot to detect a winding short circuit. The
leading edge blanking (LEB) time for short circuit
protection (LEB2) is significantly faster than the LEB time
for cycle−by−cycle protection (LEB1). Practically, if four
consecutive switching periods lead the CS pin voltage to
exceed (VCS(stop) = 150% \* VILIM), the controller enters the
auto−recovery mode (4−s operation interruption between
active bursts.)

(\\mathrm{V} _{\\mathrm{C S(s t o p p)}},150%,\*,\\mathrm{V}_{\\mathrm{I L I M}})

* * *

# NCL30086BH

S Q DRV

Q

CS R LEB1 + PWMreset

−

- Ipkmax STOP

− UVLO

VILIMIT BONOK TSD SD Pin OVP LEB2 (OVP2) + WOD\_SCP 4−pulse counter − OTP S VCS(stop) AUX\_SCP Q OFF

VCC(ovp) Q

R

4−s auto−recovery timer

**Figure 66. Winding Short Circuit Protection, Max. Peak Current Limit Circuits**

**VCC Over Voltage Protection Programmable Over Voltage Protection (OVP2)** The circuit stops generating pulses if VCC exceeds In addition to the VCC OVP protection, it is possible to VCC(OVP) and enters auto−recovery mode. This feature connect a Zener diode between VCC and the SD pin to protects the circuit in the event that the output LED string is implement programmable VCC OVP monitoring (DZ of disconnected or an individual LED in the string happens to Figure 67). The triggering level is (VZ+VOVP) where VOVP is fail open. the 2.5−V internal threshold. If this protection trips, the circuit enters the auto−recovery mode.

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NCL30086BH

Figure 67. Thermal Foldback and OVP/OTP Circuitry

* * *

# NCL30086BH

The SD pin is clamped to about 1.35 V (Vclamp) through a 1.6−k resistor (Rclamp). It is then necessary to inject about

V OVP V clamp R clamp

that is

2.50 1.35
700 A

1.6 k
typically, to trigger the OVP protection. This current helps ensure an accurate detection by using the Zener diode far from its knee region.

**Programmable Over Temperature Foldback Protection** **(OTP)** Connect an NTC between the SD pin and ground to detect an over−temperature condition. In response to a high temperature (detected if VSD drops below VTF(start)), the circuit gradually reduces the LED current down to 50% (> 50% reduction in output power) of its initial value when VSD reaches VTF(stop), in accordance with the characteristic of

Figure 68 (Note 9).

At this point, if the temperature continues to rise and the secondary OTP level is reached, (VSD drop below VOTP), the circuit enters auto−recovery mode and cannot resume operation until VSD exceeds VOTP(on) to provide some temperature hysteresis (around 10°C typically). The OTP thresholds nearly correspond to the following resistances of the NTC:

- Thermal foldback starts when RNTC£ RTF(start) (11.7 k, typically)
- Thermal foldback stops when RNTC£ RTF(stop) (8.0 k, typically)
- OTP triggers when RNTC£ ROTP(off) (5.9 k, typically) • OTP is removed when RNTC£ ROTP(on) (8.0 k, typically)
  **Figure 68. Output Current Reduction versus SD**

**Pin Voltage**

At startup, when VCC reaches VCC(on), the OTP comparator is blanked for at least 180 s which allows the SD pin voltage to reach its nominal value if a filtering capacitor is connected to the SD pin. This avoids flickering of the LED light during turn on.

**Brown−Out Protection** The NCL30086BH prevents operation when the line voltage is too low for proper operation. As sketched in

Figure 69, the circuit detects a brown−out situation if the VS

pin remains below the VBO(off) threshold (0.9 V typical) for more than the 25−ms blanking time. In this case, the controller stops operating. Operation resumes as soon as the V pin voltage exceeds VS BO(on) (1.0 V typical) and VCC is higher than VCC(on). To ease recovery, the circuit overrides the V normal sequence (no need for V cycling down CC CC below V). Instead, its consumption immediately CC(off) reduces to ICC(start) so that VCC rapidly charges up to VCC(on) and the circuit re−starts operation.

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**Figure 69. Brown−out Circuit**

9. The above mentioned initial value is the output current before the system enters the thermal foldback, that is, its maximum level if PWM or analog dimming is not engaged or a lower one based on the dimming value.
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* * *

NCL30086BH

Die Over Temperature (TSD)
The circuit stops operating if the junction temperature (TJ)

100^{\\circ}\\mathrm{C}

150^{\\circ}\\mathrm{C}

Pin Connection Faults

The circuit addresses most pin connection fault cases:
• CS Pin Short to Ground

• CS Pin Short to Ground
The circuit senses the CS pin impedance every time it

The circuit senses the CS pin impedance every time it
starts−up and after DRV pulses terminated by the 36− s
maximum on−time. If the measured impedance does
not exceed 120 typically, the circuit stops operating.
In practice, it is recommended to place a minimum of
250 in series between the CS pin and the current
sense resistor to take into account parasitics.
• Fault of the GND Connection

V\_{C C}

• Fault of the GND Connection
If the GND pin is properly connected, the supply

• Fault of the GND Connection
If the GND pin is properly connected, the supply
current drawn from the positive terminal of the VCC
capacitor, flows out of the GND pin to return to the
negative terminal of the VCC capacitor. If the GND pin
is not connected, the circuit ESD diodes offer another
return path. The accidental non−connection of the GND
pin is monitored by detecting that one of the ESD diode
is conducting. Practically, the ESD diode of CS pin is
monitored. If such a fault is detected for 200 s, the
circuit stops generating DRV pulses.
More generally, incorrect pin connection situations

Fault Management

More generally, incorrect pin connection situations
(open, grounded, shorted to adjacent pin) are covered by
ANDxxxx.

OFF Mode

The circuit turns off in the case of an incorrect feeding of the
circuit: “UVLO high”. The UVLO signal becomes high
when VCC drops below VCC(off) and remains high until
VCC exceeds VCC(on).
The circuit also turns off whenever a major faulty

V\_{C C}

The circuit also turns off whenever a major faulty
condition prevents it from operating:
• Severe OTP (V level below V)

• Severe OTP (VSD level below VOTP(off))
• V OVP

• OVP2 (additional OVP provided by SD pin)
• Output diode short circuit protection: “WOD\_SCP

• VCC OVP
• OVP2 (additional OVP provided by SD pin)

\\mathrm{V\_{C C}}

• Output diode short circuit protection: “WOD\_SCP
high”
• Output / Auxiliary winding Short circuit protection:

• Output / Auxiliary winding Short circuit protection:
“Aux\_SCP high”
• Die over temperature (TSD)

• Die over temperature (TSD)

In this mode, the DRV pulses generation is interrupted.
In the case of a latching−off fault, the circuit stops pulsing

\\mathrm{V\_{C C}}

In the case of a latching−off fault, the circuit stops pulsing
until the LED driver is unplugged and VCC drops below
VCC(reset). At that moment, the circuit resumes operation.
In the auto−recovery case, the circuit cannot generate

In the auto−recovery case, the circuit cannot generate
DRV pulses for the auto−recovery 4−s delay. When this time
has elapsed, the circuit recovers operation as soon as the
VCC voltage has exceeded VCC(on). All these protections are
auto−recovery.

\\mathrm{V\_{C C(o n)}}

ORDERING INFORMATION

| Device | Package Type | Shipping |
| --- | --- | --- |
| NCL30086BHDR2G | SOIC-8(Pb-Free/Halide Free) | 2500/Tape&Reel |

* * *

onsemi

SOIC−10 NB
CASE 751BQ
ISSUE B

\*For additional information on our Pb−Free strategy and soldering
details, please download the onsemi Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.

NOTES:

1. DIMENSIONING AND TOLERANCING PER

NOTES:

1. DIMENSIONING AND TOLERANCING PER
   ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.

ASME Y14.5M, 1994.
2\. CONTROLLING DIMENSION: MILLIMETERS.
3\. DIMENSION b DOES NOT INCLUDE DAMBAR

TERMINED AT DATUM F.
5\. DIMENSIONS A AND B ARE TO BE DETERM-
INED AT DATUM F.
6\. A1 IS DEFINED AS THE VERTICAL DISTANCE

2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
   PROTRUSION. ALLOWABLE PROTRUSION
   SHALL BE 0.10mm TOTAL IN EXCESS OF ’b’
   AT MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE

INED AT DATUM F.
6\. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.

AT MAXIMUM MATERIAL CONDITION.
4\. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS. MOLD FLASH, PROTRUSIONS, OR
GATE BURRS SHALL NOT EXCEED 0.15mm
PER SIDE. DIMENSIONS D AND E ARE DE-
TERMINED AT DATUM F.
5\. DIMENSIONS A AND B ARE TO BE DETERM-

| DOCUMENT NUMBER: | 98AON52341E | Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped“CONTROLLED COPY”in red. |  |
| --- | --- | --- | --- |
| DESCRIPTION: | SOIC-10 NB |  | PAGE 1 OF 1 |

| DIM | MILLIMETERS |  |
| --- | --- | --- |
| MIN | MAX |  |
| A | 1.25 | 1.75 |
| A1 | 0.10 | 0.25 |
| A3 | 0.17 | 0.25 |
| b | 0.31 | 0.51 |
| D | 4.80 | 5.00 |
| E | 3.80 | 4.00 |
| e | 1.00 BSC |  |
| H | 5.80 | 6.20 |
| h | 0.37 REF |  |
| L | 0.40 | 0.80 |
| L2 | 0.25 BSC |  |
| M | 0° | 8° |

XXXXX = Specific Device Code
A = Assembly Location

L = Wafer Lot
Y = Year

Y = Year
W = Work Week

W = Work Week
= Pb−Free Package

onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.

= Pb−Free Package
\*This information is generic. Please refer

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