Automotive Grade Non-Synchronous Boost Controller NCV8871 The NCV8871 is an adjustable output non−synchronous boost controller which drives an external N−channel MOSFET. The device uses peak current mode control with internal slope compensation. The IC incorporates an internal regulator that supplies charge to the gate driver. Protection features include internally−set soft−start, undervoltage Protection features include internally−set soft−start, undervoltage lockout, cycle−by−cycle current limiting, hiccup−mode short−circuit protection and thermal shutdown. Additional features include low quiescent current sleep mode and Additional features include low quiescent current sleep mode and externally−synchronizable switching frequency. Features • Peak Current Mode Control with Internal Slope Compensation • Peak Current Mode Control with Internal Slope Compensation • 1.2 V ±2% Reference voltage • 1.2 V ±2% Reference voltage • Fixed Frequency Operation • Fixed Frequency Operation • Wide Input Voltage Range of 3.2 V to 40 Vdc, 45 V Load Dump • Wide Input Voltage Range of 3.2 V to 40 Vdc, 45 V Load Dump • Input Undervoltage Lockout (UVLO) • Input Undervoltage Lockout (UVLO) • Internal Soft−Start • Internal Soft−Start • Low Quiescent Current in Sleep Mode • Low Quiescent Current in Sleep Mode • Cycle−by−Cycle Current Limit Protection • Cycle−by−Cycle Current Limit Protection • Hiccup−Mode Overcurrent Protection (OCP) • Hiccup−Mode Overcurrent Protection (OCP) • Hiccup−Mode Short−Circuit Protection (SCP) • Thermal Shutdown (TSD) • NCV Prefix for Automotive and Other Applications Requiring • Hiccup−Mode Short−Circuit Protection (SCP) • Thermal Shutdown (TSD) • NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable • This is a Pb−Free Device • This is a Pb−Free Device SOIC−8 D SUFFIX CASE 751 MARKING DIAGRAM 8871xxG = Specific Device Code xx = 00, 03, 04, 05 A = Assembly Location A = Assembly Location L = Wafer Lot L = Wafer Lot Y = Year Y = Year W = Work Week W = Work Week = Pb−Free Package = Pb−Free Package PIN CONNECTIONS ORDERING INFORMATION | Device | Package | Shipping $ ^{\\dagger}$ | | --- | --- | --- | | NCV887100D1R2G | SOIC-8(Pb-Free) | 2500/Tape&Reel | | NCV887103D1R2G | SOIC-8(Pb-Free) | 2500/Tape&Reel | | NCV887104D1R2G | SOIC-8(Pb-Free) | 2500/Tape&Reel | | NCV887105D1R2G | SOIC-8(Pb-Free) | 2500/Tape&Reel | †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. * * * NCV8871 Figure 1. Simplified Block Diagram and Application Schematic PACKAGE PIN DESCRIPTIONS | Pin No. | Pin Symbol | Function | | --- | --- | --- | | 1 | EN/SYNC | Enable and synchronization input. The falling edge synchronizes the internal oscillator. The part is disabled into sleep mode when this pin is brought low for longer than the enable time-out period. | | 2 | ISNS | Current sense input. Connect this pin to the source of the external N-MOSFET, through a current-sense resistor to ground to sense the switching current for regulation and current limiting. | | 3 | GND | Ground reference. | | 4 | GDRV | Gate driver output. Connect to gate of the external N-MOSFET. A series resistance can be added from GDRV to the gate to tailor EMC performance. | | 5 | VDRV | Driving voltage. Internally-regulated supply for driving the external N-MOSFET, sourced from VIN. Bypass with a 1.0 μF ceramic capacitor to ground. | | 6 | VIN | Input voltage. If bootstrapping operation is desired, connect a diode from the input supply to VIN, in addition to a diode from the output voltage to VDRV and/or VIN. | | 7 | VC | Output of the voltage error amplifier. An external compensator network from VC to GND is used to stabilize the converter. | | 8 | VFB | Output voltage feedback. A resistor from the output voltage to VFB with another resistor from VFB to GND creates a voltage divider for regulation and programming of the output voltage. | * * * NCV8871 ABSOLUTE MAXIMUM RATINGS (Voltages are with respect to GND, unless otherwise indicated) | Rating | Value | Unit | | --- | --- | --- | | Dc Supply Voltage(VIN) | -0.3 to 40 | V | | Peak Transient Voltage(Load Dump on VIN) | 45 | V | | Dc Supply Voltage(VDRV,GDRV) | 12 | V | | Peak Transient Voltage(VFB) | -0.3 to 6 | V | | Dc Voltage(VC,VFB,ISNS) | -0.3 to 3.6 | V | | Dc Voltage(EN/SYNC) | -0.3 to 6 | V | | Dc Voltage Stress(VIN-VDRV)\* | -0.7 to 45 | V | | Operating Junction Temperature | -40 to 150 | $^{\\circ}C}$ | | Storage Temperature Range | -65 to 150 | $^{\\circ}C}$ | | Peak Reflow Soldering Temperature:Pb-Free,60 to 150 seconds at $217^{\\circ}C$ | 265 peak | $^{\\circ}C}$ | ^circ\ \\mathrm{C} ^circ\ \\mathrm{C} 217^{\\circ}\\mathrm{C} ^{\\circ}\\mathrm{C} Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. \*An external diode from the input to the VIN pin is required if bootstrapping VDRV and VIN off of the output voltage. PACKAGE CAPABILITIES | Characteristic | | Value | Unit | | --- | --- | --- | --- | | ESD Capability(All Pins) | Human Body Model | ≥2.0 | kV | | Machine Model | ≥200 | V | | | Moisture Sensitivity Level | | 1 | - | | Package Thermal Resistance | Junction-to-Ambient，RθJA(Note 1) | 100 | °C/W | \\mathsf{R}\_{\\mathsf{U J A}} 1. 1 in2, 1 oz copper area used for heatsinking. \ n^{2} The NCV8871 features several variants to better fit a multitude of applications. The table below shows the typical values of parameters for the parts that are currently available. | Part No. | Dmax | fs | tss | Sa | Vcl | Isrc | Isink | VDRV | SCE | | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | | NCV887100 | 88% | 170kHz | 7.4ms | 53mV/μs | 400mV | 800mA | 600mA | 10.5V | Y | | NCV887103 | 93% | 340kHz | 3.7ms | 53mV/μs | 200mV | 575mA | 350mA | 8.4V | Y | | NCV887104 | 93% | 340kHz | 3.7ms | 53mV/μs | 200mV | 800mA | 600mA | 8.4V | N | | NCV887105 | 88% | 170kHz | 7.4ms | 53mV/μs | 400mV | 800mA | 600mA | 10.5V | N | \\mathbf{D}\_{\\mathsf{m a x}} \ {tt f f}\_{\\mathrm{s}} \\mathbf{t\_{s s}} {\\bf s\_\_a{a}} \\nabla\_{\\mathbf{c l}} \ \_{s i n k} \\mathsf{D}\_{\\mathsf{m a x}} {\\sf{f}}\_{\\mathrm{s}} | Symbol | Characteristic | Symbol | Characteristic | Symbol | Characteristic | | --- | --- | --- | --- | --- | --- | | Dmax | Maximum Duty Cycle | fs | Switching Frequency | tss | Soft-Start Time | | Sa | Slope Compensating Ramp | Vcl | Current Limit Trip Voltage | Isrc | Gate Drive Sourcing Current | | Isink | Gate Drive Sinking Current | VDRV | Drive Voltage | SCE | Short Circuit Enable | \\mathbf{S\_{a}} \ \_{\\mathrm{s s}} \ \_{s i k k} \ mathrm V{}\_{\\mathrm{c}}\| \\mathsf{l}\_{\\mathrm{s r c}} * * * NCV8871 ELECTRICAL CHARACTERISTICS (−40°C < TJ< 150°C, 3.2 V < VIN < 40 V, unless otherwise specified) Min/Max values are guaranteed by test, design or statistical correlation. \\mathsf{V}<\\mathsf{V}\_{\ \ 1\\mathsf{N}}<40,\\mathrm{V} (-40^{\\circ}C<\_J155^^{\\circ}C, | Characteristic | Symbol | Conditions | Min | Typ | Max | Unit | | --- | --- | --- | --- | --- | --- | --- | | Quiescent Current,Sleep Mode | Iq,sleep | VIN=13.2V,EN=0,TJ=25℃ | - | 2.0 | - | μA | | --- | --- | --- | --- | --- | --- | --- | | Quiescent Current,Sleep Mode | Iq,sleep | VIN=13.2V,EN=0,-40℃＜TJ＜125℃ | - | 2.0 | 6.0 | μA | | Quiescent Current,No switching | Iq,off | Into VIN pin,EN=1,No switching | - | 1.5 | 2.5 | mA | | Quiescent Current,Switching,normal operation | Iq,on | Into VIN pin,EN=1,Switching | - | 3.0 | 6.0 | mA | \ \_{\\mathtt{q,s l e e p}} V\_{N}=13.2V,E N=0,T\_{J}=25^{\\circ}C \ \_{\\mathtt{q,s l e e p}} V\_{N}=13.2V,E N=0.-40^CVUVLO | 2.0 | - | 5.0 | V | | EN/SYNC input low voltage | Vs,il | | 0 | - | 800 | mV | | EN/SYNC time-out ratio | %ten | From SYNC falling edge,to oscillator control(EN high)or shutdown(EN low),Percent of typical switching period | - | - | 350 | % | | SYNC minimum frequency ratio | %f sync,min | Percent offs | - | - | 80 | % | | SYNC maximum frequency | f sync,max | | 1.1 | - | - | MHz | | Synchronization delay | ts,dly | From SYNC falling edge to GDRV falling edge under open loop conditions | - | 50 | 100 | ns | | Synchronization duty cycle | Dsync | | 25 | - | 75 | % | | CURRENT SENSE AMPLIFIER | | | | | | | \\mathsf{V}\_{\\mathsf{E N/S Y N C}}=5,\\mathsf{V} \\mathsf{V}\_{\\mathrm{s,i h}} \\mathsf{V}\_{\\mathrm{s,i}}\\mathrm{{i}}}} \\mathsf{V} _{\\mathsf{I N}}>\\mathsf{V}_{\\mathsf{U V L O}} | Low-frequency gain | Acsa | Input-to-output gain at dc, ISNS≤1V | 0.9 | 1.0 | 1.1 | V/V | | --- | --- | --- | --- | --- | --- | --- | | Bandwidth | BWcsa | Gain of Acsa-3dB | 2.5 | - | - | MHz | | ISNS input bias current | Isns,bias | Out of ISNS pin | - | 30 | 50 | μA | | Current limit threshold voltage | Vcl | Voltage on ISNS pin | | | | mV | | NCV887100 | 360 | 400 | 440 | | | | | NCV887103 | 180 | 200 | 220 | | | | | NCV887104 | 180 | 200 | 220 | | | | | NCV887105 | 360 | 400 | 440 | | | | | Current limit, Response time | tcl | CL tripped until GDRV falling edge, VISNS=Vcl(typ)+60mV | - | 80 | 125 | ns | \\sf{f}\\Delta\_{c s a}-3sf\ d \\mathsf{f}\_{\\mathsf{s y n c,m a x}} \ mathrm V{}\_{\\mathrm{c l}} \\mathfrak{t}\_{\\mathrm{s}d,\\mathrm{d}}y \\up{{\\bf f}}\_{\\mathrm{s}} \\mathfrak{f}\_{\\mathrm{c}}\| * * * NCV8871 -40^CT\_{sd}$ to stop switching | - | - | 100 | ns | {\\sf{T}}\_{\\mathrm{s d}} \ mathrm{^\\circ\\mathrm C} \\tau\_{\\mathbf{J}} {\\sf T}\_{\\sf s d,h y s} ^{\\circ}\\mathrm{C} \ {\\boldsymbol{\\tau}}{\\boldsymbol{\\up{}}} \\mathsf{t}\_{\\mathsf{s d},\\mathsf{d l y}} \\sf{T} _{J}>T_{s d} Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. * * * # NCV8871 ## TYPICAL PERFORMANCE CHARACTERISTICS 7 TJ = 25°C A) 6 5 4 3 , SLEEP CURRENT (2 I q,sleep 1 0 VIN, INPUT VOLTAGE (V) **Figure 2. Sleep Current vs. Input Voltage** 6 VIN = 13.2 V A) 5 4 3 2 , SLEEP CURRENT ( I q,sleep 1 0 −50 0 50 100 150 200 TJ, JUNCTION TEMPERATURE (°C) **Figure 4. Sleep Current vs. Temperature** 119 MINIMUM ON TIME (ns) 117 t on,min 115 −40 10 60 110 160 TJ, JUNCTION TEMPERATURE (°C) **Figure 6. Minimum On Time vs. Temperature** 5.5 5.0 4.5 4.0 , QUIESCENTCURRENT (mA) TJ = 25°C, I q,on VIN = 13.2 V 3.5 fs, SWITCHING FREQUENCY (kHz) **Figure 3. Quiescent Current vs. Switching** **Frequency** 3.30 VIN = 13.2 V 3.25 fs = 170 kHz 3.20 3.15 3.10 , QUIESCENTCURRENT (mA)3.05 I q,on 3.00 −40 10 60 110 160 TJ, JUNCTION TEMPERATURE (°C) **Figure 5. Quiescent Current vs. Temperature** 1.010 °C) 1.005 1.000 0.995 NORMALIZED CURRENT LIMIT (25 0.990 −40 10 60 110 160 TJ, JUNCTION TEMPERATURE (°C) **Figure 7. Normalized Current Limit vs.** **Temperature** 0102030400 200 400 600 800 1000 **[www.onsemi.com](/content/site-root.html)** * * * TYPICAL PERFORMANCE CHARACTERISTICS TJ, JUNCTION TEMPERATURE (°C) Figure 8. Reference Voltage vs. Temperature Figure 9. Enable Pulldown Current vs. Voltage TJ, JUNCTION TEMPERATURE (°C) Figure 10. Enable Pulldown Current vs. Temperature * * * NCV8871 THEORY OF OPERATION Figure 11. Current Mode Control Schematic Current Mode Control The NCV8871 incorporates a current mode control Current Mode Control The NCV8871 incorporates a current mode control scheme, in which the PWM ramp signal is derived from the power switch current. This ramp signal is compared to the output of the error amplifier to control the on−time of the power switch. The oscillator is used as a fixed−frequency clock to ensure a constant operational frequency. The resulting control scheme features several advantages over conventional voltage mode control. First, derived directly from the inductor, the ramp signal responds immediately to line voltage changes. This eliminates the delay caused by the output filter and the error amplifier, which is commonly found in voltage mode controllers. The second benefit comes from inherent pulse−by−pulse current limiting by merely clamping the peak switching current. Finally, since current mode commands an output current rather than voltage, the filter offers only a single pole to the feedback loop. This allows for a simpler compensation. The NCV8871 also includes a slope compensation The NCV8871 features two current limit protections, peak current mode and over current latch off. When the current sense amplifier detects a voltage above the peak current limit between ISNS and GND after the current limit leading edge blanking time, the peak current limit causes the power switch to turn off for the remainder of the cycle. Set the current limit with a resistor from ISNS to GND, with R = VCL / Ilimit. Current Limit The NCV8871 features two current limit protections, =\\mathsf{V} _{\\mathrm{C L}},/,\\mathrm{I}_{\\mathrm{l i m i t}} If the voltage across the current sense resistor exceeds the over current threshold voltage the device enters over current hiccup mode. The device will remain off for the hiccup time and then go through the soft−start procedure. Short Circuit Protection If the short circuit enable bit is set (SCE = Y) the device If the short circuit enable bit is set (SCE = Y) the device will attempt to protect the power MOSFET from damage. When the output voltage falls below the short circuit trip voltage, after the initial short circuit blanking time, the device enters short circuit latch off. The device will remain off for the hiccup time and then go through the soft−start. As VIN ramps up from 0 V, and EN/SYNC is low (0 V), all die internal voltage rails are normally 0 V. If VIN of sufficient amplitude and a high slew rate is applied, these internal voltage rails may elevate momentarily due to die parasitic coupling. Elevation of the rails can inadvertently cause an internal power−on reset (POR) circuit and some internal logic to momentarily activate. With EN/SYNC is EN/SYNC The Enable/Synchronization pin has three modes. When a dc logic high (CMOS/TTL compatible) voltage is applied to this pin the NCV8871 operates at the programmed frequency. When a dc logic low voltage is applied to this pin the NCV8871 enters a low quiescent current sleep mode. When a square wave of at least %fsync,min of the free running switching frequency is applied to this pin, the switcher operates at the same frequency as the square wave. If the signal is slower than this, it will be interpreted as enabling and disabling the part. The falling edge of the square wave corresponds to the start of the switching cycle. If device is disabled, it must be disabled for 42 s before being re−enabled. As VIN ramps up from 0 V, and EN/SYNC is low (0 V), EN/SYNC The Enable/Synchronization pin has three modes. When * * * NCV8871 held low during VIN ramp, the internal voltage rails and the POR circuit will decay down to 0 V. If EN/SYNC asserts high before decay of the POR circuit, the logic could become stuck in an invalid state (no switching). To avoid the possibility for such a power up issue, the EN/SYNC signal should be applied a minimum of 500 s after application of voltage on VIN. If the VIN pin voltage falls below VUVLO when If the VIN pin voltage falls below VUVLO when EN/SYNC pin is at logic−high, the IC may not power up when VIN returns back above the UVLO. To resume a normal operating state, the EN/SYNC pin must be cycled with a single logic−low to logic−high transition. \\mathrm{V\_{U V L0}} UVLO Input Undervoltage Lockout (UVLO) is provided to UVLO Input Undervoltage Lockout (UVLO) is provided to ensure that unexpected behavior does not occur when VIN is too low to support the internal rails and power the controller. The IC will start up when enabled and VIN surpasses the UVLO threshold plus the UVLO hysteresis and will shut down when VIN drops below the UVLO threshold or the part is disabled. To avoid any lock state under UVLO conditions, the To avoid any lock state under UVLO conditions, the EN/SYNC pin should be in logic−low state. For further details, please refer to EN/SYNC paragraph. Internal Soft−Start To insure moderate inrush current and reduce output Internal Soft−Start To insure moderate inrush current and reduce output overshoot, the NCV8871 features a soft start which charges a capacitor with a fixed current to ramp up the reference voltage. This fixed current is based on the switching frequency, so that if the NCV8871 is synchronized to twice the default switching frequency the soft start will last half as long. VDRV VDRV An internal regulator provides the drive voltage for the An internal regulator provides the drive voltage for the gate driver. Bypass with a ceramic capacitor to ground to ensure fast turn on times. The capacitor should be between 0.1 F and 1 F, depending on switching speed and charge requirements of the external MOSFET. 1. Define Operational Parameters 2. Select Current Sense Resistor 0.1,\\upmu 3. Select Output Inductor 4. Select Output Capacitors 5. Select Current Sense Resistor 6. Select Output Inductor Design Methodology This section details an overview of the component selection process for the NCV8871 in continuous conduction mode boost. It is intended to assist with the design process but does not remove all engineering design work. Many of the equations make heavy use of the small ripple approximation. This process entails the following steps: 1. Define Operational Parameters 1~\\upmu\\mathbf{F}, 4. Select Output Capacitors 5. Select Input Capacitors 6. Select Feedback Resistors 7. Select Feedback Resistors 8. Select Compensator Components 9. Select Compensator Components 10. Select MOSFET(s) Design Methodology This section details an overview of the component selection 8. Select MOSFET(s) 9. Determine Feedback Loop Compensation Network 10. Select Diode 11. Determine Feedback Loop Compensation Network 12. Define Operational Parameters Before beginning the design, define the operating Before beginning the design, define the operating parameters of the application. These include: VIN(min): minimum input voltage \[V\] VIN(min): minimum input voltage \[V\] VIN(max): maximum input voltage \[V\] VIN(max): maximum input voltage \[V\] VOUT: output voltage \[V\] \\mathrm{V}{}\_{\\mathrm{I N}(m a x)} \\mathrm{V\_{O U T}}} VOUT: output voltage \[V\] IOUT(max): maximum output current \[A\] IOUT(max): maximum output current \[A\] ICL: desired typical cycle-by-cycle current limit \[A\] ICL: desired typical cycle-by-cycle current limit \[A\] From this the ideal minimum and maximum duty cycles can be calculated as follows: \\sf D\_{m i n}=1-\\frac{V\_{I N(m a x)}}{V\_{O U T}} \\sf D\_{m a x}=1-\\frac{V\_{I N(m i n)}}{V\_{O U T}} \\mathrm{D\_{m a x}} Both duty cycles will actually be higher due to power loss in the conversion. The exact duty cycles will depend on conduction and switching losses. If the maximum input voltage is higher than the output voltage, the minimum duty cycle will be negative. This is because a boost converter cannot have an output lower than the input. In situations where the input is higher than the output, the output will follow the input, minus the diode drop of the output diode and the converter will not attempt to switch. If the calculated Dmax is higher the Dmax of the NCV8871, If the calculated Dmax is higher the Dmax of the NCV8871, the conversion will not be possible. It is important for a boost converter to have a restricted Dmax, because while the ideal conversion ration of a boost converter goes up to infinity as D approaches 1, a real converter’s conversion ratio starts to decrease as losses overtake the increased power transfer. If the converter is in this range it will not be able to regulate properly. If the following equation is not satisfied, the device will \\mathrm{D}\_{\\mathrm{m a x}}, \\mathrm{\_m m a x} If the following equation is not satisfied, the device will skip pulses at high VIN: \\frac{\\mathsf{D} _{\\mathsf{m i n}}}{f_{\\mathsf{s}}}\\geq t\_{\\mathsf{o n}(\\mathsf{m i n})} Where: fs: switching frequency \[Hz\] ton(min): minimum on time \[s\] Current sensing for peak current mode control and current limit relies on the MOSFET current signal, which is measured with a ground referenced amplifier. The easiest method of generating this signal is to use a current sense resistor from the source of the MOSFET to device ground. The sense resistor should be selected as follows: V \\mathbf{f}\_{\\mathrm{s}} 2. Select Current Sense Resistor Current sensing for peak current mode control and current * * * NCV8871 Where: RS: sense resistor \[\] VCL: current limit threshold voltage \[V\] VCL: current limit threshold voltage \[V\] ICL: desire current limit \[A\] \\mathrm{V\_{C L}} ICL: desire current limit \[A\] 3. Select Output Inductor The output inductor controls the current ripple that occurs The output inductor controls the current ripple that occurs over a switching period. A high current ripple will result in excessive power loss and ripple current requirements. A low current ripple will result in a poor control signal and a slow current slew rate in case of load steps. A good starting point for peak to peak ripple is around 20−40% of the inductor current at the maximum load at the worst case VIN, but operation should be verified empirically. The worst case VIN is half of VOUT, or whatever VIN is closest to half of VOUT. After choosing a peak current ripple value, calculate the inductor value as follows: \\mathrm{V N.} \\mathrm{V}\_{\\mathrm{N N}} \\mathrm{V\_{r e f}} \\mathrm{V\_{O U T}} \\mathrm{V\_\_{N}} \\mathrm{V\_{O U T}} \\mathsf{L}=\\frac{\\mathsf{V} _{\\mathsf{I N(W C)}}\\mathsf{D}_{\\mathsf{W C}}}{\\Delta\\mathsf{I} _{\\mathsf{L,m a x}}\ f_{\\mathsf{s}}} Where: VIN(WC): VIN value as close as possible to half of VOUT \[V\] DWC: duty cycle at VIN(WC) \\mathrm{V\_{N\\mathrm{}}} \\mathrm{V\_{0T T}}\ V\ \\mathrm{D\_{W C}}\ \ {tt{d u}y,}\ {{mathrm{c c c l e}}}\ {\\mathrm{a t}},{\\mathsf{V}{\_{N(W C)}}} DWC: duty cycle at VIN(WC) IL,max: maximum peak to peak ripple \[A\] The maximum average inductor current can be calculated \\Delta\\mathrm{I}\_{\\mathrm{L}m a x}. The maximum average inductor current can be calculated as follows: V I \\mathsf{I} _{\\mathsf{L},\\mathsf{A V G}}=\\frac{\\mathsf{V}_{\\mathsf{O U T}}\\mathsf{I} _{\\mathsf{O U T}(\\mathsf{m a x})}}{\\mathsf{V}_{\\mathsf{I N}(\\mathsf{m i n})}\\mathsf{n}} The Peak Inductor current can be calculated as follows: I \\mathsf I\_{\\mathsf L,\\mathsf p e a k}=\\mathsf I\_{\\mathsf L,\\mathsf v a\\mathsf}+\\frac{\\Delta\\mathsf I\_{\\mathsf L,\\mathsf m a m}}{2} Where: IL,peak: Peak inductor current value \[A\] \\mathrm{I\_{L,p e a k}}. 4. Select Output Capacitors The output capacitors smooth the output voltage and The output capacitors smooth the output voltage and reduce the overshoot and undershoot associated with line transients. The steady state output ripple associated with the output capacitors can be calculated as follows: V 5. Select Input Capacitors The input capacitor reduces voltage ripple on the input to the module associated with the ac component of the input current. The capacitors need to survive an RMS ripple current as follows: \\begin{array}{r l}&{\\mathsf{I} _{\ u o u(\\mathsf{R M S})}=\\mathsf{I}_{\\mathsf{O M T}}\\sqrt{\\frac{\\mathsf{D} _{\\mathsf{W C}}}{\\mathsf{D}_{\\mathsf{W C}}^{\\prime}}+\\frac{\\mathsf{D} _{\\mathsf{W C}}}{1mathsf2}\\left(\\frac{\\mathsf{D}{\ }_{\\mathsf{W C}}^{\\prime}}{\\mathsf{R}\_{\\mathsf{W O T}}^{\\prime}\ mathsf T S S}\\right)^{2}}}\ &{\\quad\\mathsf{h e ~~u s e~~ o f ~~p a r a l l e l~~ c e r a i n ~~b y p a s s~~ c a p a c i t o r s ~~i s~~ s t r o n g}}\\end{array} \\sf\_C i n(R M S)=\\frac{V\_{1N(m i n)}^{2},D\_{W C}}{L\_{S}V\_{O U T}^{2}\\sqrt{3}} 6. Select Feedback Resistors The feedback resistors form a resistor divider from the The feedback resistors form a resistor divider from the output of the converter to ground, with a tap to the feedback pin. During regulation, the divided voltage will equal Vref. The lower feedback resistor can be chosen, and the upper feedback resistor value is calculated as follows: \\mathsf{R} _{\\mathsf{u p p e r}}=\\mathsf{R}_{\\mathsf{l o w e r}}\\frac{\\left(\\mathsf{V} _{\\mathsf{o u t}}-\\mathsf{V}_{\\mathsf{r e f}}\\right)}{\\mathsf{V}\_{\\mathsf{r e f}}} The total feedback resistance (Rupper + Rlower) should be in the range of 1 k – 100 k. (\\mathrm{R} _{\\tt{u p p e r}}+\\mathrm{R}_{\\tt{l o w e r}}) 7. Select Compensator Components Current Mode control method employed by the NCV8871 Current Mode control method employed by the NCV8871 allows the use of a simple, Type II compensation to optimize the dynamic response according to system requirements. 8. Select MOSFET(s) In order to ensure the gate drive voltage does not drop out In order to ensure the gate drive voltage does not drop out the MOSFET(s) chosen must not violate the following inequality: \\tt{Q} _{g(t o t a l)}\\leq\\frac{l_{d n}}{f\_{s}} Where: Qg(total): Total Gate Charge of MOSFET(s) \[C\] Idrv: Drive voltage current \[A\] fs: Switching Frequency \[Hz\] \\mathrm{Q}{}\_{\\mathrm{g(t o t a l)}} \\mathrm{I}\_{\\mathrm{d r V}} drv fs: Switching Frequency \[Hz\] The maximum RMS Current can be calculated as follows: The maximum RMS Current can be calculated as follows: \\mathbf{f}\_{\\mathrm{s}}.dot}{\\mathbf{i} 1\_{Q(m a x)}=I\_{o u t}\\frac{D}{D^{\\prime}} The maximum voltage across the MOSFET will be the maximum output voltage, which is the higher of the maximum input voltage and the regulated output voltaged: V V \\mathsf{V} _{\\mathsf{Q}(\\mathsf{m a x})}=\\mathsf{V}_{\\mathsf{O U T}(\\mathsf{m a x})} 9. Select Diode The output diode rectifies the output current. The average The output diode rectifies the output current. The average current through diode will be equal to the output current: I I \\mathsf{V} _{\\mathsf{D}(\\mathsf{m a x})}=\\mathsf{V}_{\\mathsf{O U T}(\\mathsf{m a x})} Where: Pd: Power dissipation in the diode \[W\] Vf(max): Maximum forward voltage of the diode \[V\] Vf(max): Maximum forward voltage of the diode \[V\] * * * NCV8871 10. Determine Feedback Loop Compensation Network The purpose of a compensation network is to stabilize the 11. Determine Feedback Loop Compensation Network The purpose of a compensation network is to stabilize the dynamic response of the converter. By optimizing the compensation network, stable regulation response is achieved for input line and load transients. Compensator design involves the placement of poles and Compensator design involves the placement of poles and zeros in the closed loop transfer function. Losses from the boost inductor, MOSFET, current sensing and boost diode losses also influence the gain and compensation expressions. The OTA has an ESD protection structure (RESD ≈ 502, data not provided in the datasheet) located on the die between the OTA output and the IC package compensation pin (VC). The information from the OTA PWM feedback control signal (VCTRL) may differ from the IC-VC signal if R2 is of similar order of magnitude as RESD. The compensation and gain expressions which follow take influence from the OTA output impedance elements into account. (R\_{E\\mathit D D}\\approx502;\\Omega, R\_{E S D} Type-I compensation is not possible due to the presence of RESD. The Figures 12 and 13 compensation networks correspond to a Type-II network in series with RESD. The resulting control-output transfer function is an accurate mathematical model of the IC in a boost converter topology. The model does have limitations and a more accurate SPICE model should be considered for a more detailed analysis: • The attenuating effect of large value ceramic capacitors R\_{2} R\_{E S D} • The attenuating effect of large value ceramic capacitors in parallel with output electrolytic capacitor ESR is not considered in the equations. • The CCM Boost control-output transfer function • The CCM Boost control-output transfer function includes operating efficiency as a correction factor to improve modeling accuracy under low input voltage and high output current operating conditions where operating losses becomes significant. Figure 12. NCV8871 Boost Converter OTA and Compensation * * * # NCV8871 VIN Vd VOUT 1:N r Cf Lp ROUT Rds(on) COUT VC GDRV R2 **RESD** C2 ISNS C1 **VCTRL** **OTA** Ri R0 **VREF** ## VFB R1 GND R low **Figure 13. NCV8871 Flyback Converter OTA and Compensation** The following equations may be used to select compensation Necessary equations for describing the modulator gain components R2, C1, C2 for Figures 12 & 13 power supply. (Vctrl-to-Vout gain) Hctrl\_output(f) are described next. Boost Required input design parameters for analysis are: continuous conduction mode (CCM) and discontinuous _Vd = Output diode Vf (V)_ conduction mode (DCM) transfer function expressions are summarized in Table 1. Flyback CCM and DCM transfer _VIN = Power supply input voltage (V)_ function expressions are summarized in Table 2. _N = Ns/Np (Flyback transformer turns ratio)_ _Ri = Current sense resistor (_) _RDS(on) = MOSFET RDS(on) (_) (Rsw\_eq = RDS(on) + Ri for the boost continuous conduction mode (CCM) expressions) _COUT = Bulk output capacitor value (F)_ _rCF = Bulk output capacitor ESR (_) _ROUT = Equivalent resistance of output load (_) _Pout = Output Power (W)_ _L = Boost inductor value or flyback transformer primary_ side inductance (H) _rL = Boost inductor ESR (_) _Ts = 1/fs, where fs = clock frequency (Hz)_ _R1 and Rlow = Feedback resistor divider values used to set the_ output voltage () _VOUT = Device specific output voltage (defined by R1 and_ Rlow values) (V) _R0 = OTA output resistance = 3 M_ _Sa = IC slope compensation (e.g. 53 mV/_ s for NCV887100) _gm = OTA transconductance = 1.2 mS_ D = Controller duty ratio D’ = 1 − D **[www.onsemi.com](/content/site-root.html)** * * * NCV8871 Table 1. BOOST CCM AND DCM TRANSFER FUNCTION EXPRESSIONS | | CCM | DCM | | --- | --- | --- | | Duty Ratio(D) | \[2ROUTVdVIN-\[Rswcq+ROUT(VIN/VOUT-2)\]VOUT2-VOUT√(ROUT(ROUTVIN2+2RswcqVINVOUT-4VdRswcqVIN-4LVIN2)+Rswcq2VOUT2)/2ROUT(VOUT2+VdVIN\] | $\\sqrt{2\\tau L(M)}$Where: $\\tau\_{L}=\\frac{\\pi}{2}$ | | VOUTVINDC Voltage Gain(M) | $\\frac{1}{1-D}\\left\[1-\\frac{(1-D)Vd}{Vout}\\right\]\\left\[\\frac{1}{1+\\frac{1}{(1-D)^2\\left(\\frac{r\_L+DRswcq}{ROUT}\\right)}}\\right\]$ | $\\frac{1}{2}\\left(1+\\sqrt{1}\\right)$ | | Inductor On-slope($S\_{n}$), V/s | $\\frac{VIN-I\_{\\text{Lave}}(r\_{L}+Rswcq)}{L}R\_{i}$Where average inductor current: $I\_{\\text{Lave}}=\\frac{P\_{\\text{out}}}{VIN\\eta}$ | $\\frac{VIN}{L}R\_{i}$ | | Compensation Ramp ($m\_{c}$) | $1+\\frac{S\_{n}}{S\_{n}}$ | $1+\\frac{S\_{n}}{S\_{n}}$ | | Cout ESR Zero($\\omega\_{z1}$) | $\\frac{1}{rCF COUT}$ | $\\frac{1}{rCF COUT}$ | | Right-Half-Plane Zero($\\omega\_{z2}$) | $\\frac{(1-D)^{2}}{L}(R\_OUT-\\frac{rCF ROUT}{rCF+R\_OUT})-\\frac{rL}{L}$ | $\\frac{R\_OUT}{M^{2}L}$ | | Low Frequency Modulator Pole($\\omega\_{p1}$) | $\\frac{2}{R\_OUT}+\\frac{T\_{s}}{LM^{3}}m\_{c}$COUT | $\\frac{1}{RCF COUT}$ | | High Frequency Modulator Pole($\\omega\_{p2}$) | - | $2F\_{SW}\\left(\\frac{1}{L}\\right)$ | | Sampling Double Pole($\\omega\_{n}$) | $\\frac{\\pi}{T\_{s}}$ | - | | Sampling Quality Coefficient($Q\_{p}$) | $\\frac{1}{\\pi(m\_{c}(1-D)-0.5)}$ | - | | $F\_{m}$ | $\\frac{1}{2M+\\frac{R\_OUT}{LM^{2}}\\left(\\frac{1}{2}+\\frac{S\_{n}}{S\_{n}}\\right)}$ | $\\frac{1}{S\_{n}m\_{c}}$ | | $H\_{d}$ | $\\frac{\\eta R\_{OUT}}{R\_{i}}$ | $\\frac{2V\_{OUT}}{D}-\\frac{M}{2}$ | | Control-Output Transfer Function($H\_{\\text{ctrl\_output}}(\\theta)$) | $\\frac{\\left(1+j\\frac{2\\pi f}{o\_{w1}}\\right)\\left(1-j\\frac{2\\pi f}{o\_{w2}}\\right)}{F\_{m}H\_{d}}\\frac{\\left(1+j\\frac{2\\pi f}{o\_{w1}}\\right)\\left(1+j\\frac{2\\pi f}{o\_{w2}}\\right)}{F\_{m}H\_{d}}\\left(1+j\\frac{2\\pi f}{o\_{w1}}\\right)\\left(1+j\\frac{2\\pi f}{o\_{w2}}\\right)}$ | $F\_{m}H\_{d}\\left(1+j\\frac{2\\pi f}{o\_{w1}}\\right)\\left(1+j\\frac{2\\pi f}{o\_{w2}}\\right)$ | \\mathrm{2R\_{O U T}V\_{d}V\_{I N}-\\left\[R\_{s w\_c q}+R\_{O U T}\\bigg(\\frac{V\_{I N}}{V\_{O U T}}-2\\bigg)\\right\]V\_{O U T}^{2}} \\lefted{-\\mathrm{v} _{\\mathrm{O U T}}\\sqrt{\\mathrm{R}_{\\mathrm{O U T}}\\left(\\begin{matrix}{\\mathrm{R} _{\\mathrm{O U T}}\\mathrm{V}_{\\mathrm{R R}}^{2}+2\\mathrm{R} _{\\mathrm{w w},\\mathrm{c q}}\\mathrm{V}_{\\mathrm{R W}}\\mathrm{V} _{\\mathrm{O U T}}-4\\mathrm{V}_{\\mathrm{d}}\\mathrm{R} _{\\mathrm{w w},\\mathrm{c q}}\\mathrm{V}_{\\mathrm{N U}}^{2}}\ {-4\\mathrm{R} _{\\mathrm{w w},\\mathrm{c q}}\\mathrm{V}_{\\mathrm{O U T}}^{2}-4\\mathrm{r} _{\\mathrm{T}}\\mathrm{V}_{\\mathrm{Q U T}}-mathrm44\\mathrm{r} _{\\mathrm{L}}\\mathrm{V}_{\\mathrm{O U T}}^mathrm{V}}{2}}\\end{matrix}\\right)+\\mathrm{R} _{\\mathrm{w w},\\mathrm{q}}\\mathrm{q}mathrm{\\mathrm{Q U}}}^mathrm{22}mathrm{\ V_{\\mathrm{O U T}}}{}^ \\sqrt{2\\uptau\_{\\mathrm{L}}\\mathbf{M}(\\mathbf{M}\\mathrm{ ~~-~~}1)} \ \ 2!\\tt R{} _{{O T T}}\ {left{({{V}{{0}}{{U T}}^{2}}+{{{V}}_{d}}{{{V}}\_{I N}}}\\right)} V\_{0u U}}/\_{N} \\frac{1}{1,-,\\mathrm{D}}\\left\[1,-,\\frac{\\left((1,\ --,\\mathrm{D}\\right)\\mathrm{V} _{\\mathrm{d}}}{\\mathrm{V}_{\\mathrm{o u t}}}\\right\],\\left(\\frac{1}{1,+,\\frac{1}{\\left(1-\\mathrm{D}\\right)^{2}\\left(\\frac{\\mathrm{r} _{\\mathrm{L}}+\\mathrm{D}\\mathrm{R}_{\\mathrm{s w,,q}}}{\\mathrm{R}\_{\\mathrm{O U T}}}\\right)}}\\right\] \\frac{1}{2}\\left(1,+,\\sqrt{1+\\frac{2\ {bf D D}^{2}}{{\\tt}!\_{!L}}}\\right) (\\mathsf{S}\_{n}),\\mathsf{V}/\\mathsf{S} \\frac{V\_{I\\mathrm{N}}-\_I mathrm{L a v e}\\bigl(r\_{L}+\ R R\_{W\_e q}\\bigr)}{L}R\_\_{\\mathrm{i}} \\frac{\\mathrm{v\_{I N}}}{\\mathrm{L}}\\mathrm{R\_{i}} \\mathrm{I\_{L a v e},=,\\frac{P\_{o u t}}{V\_{I N}\\upeta}} (m\_{c}) 1,\\mathrm{+},{\\frac{S\_{a}}{S\_{n}}} \\begin{array}{l}{\\mathsf{C\_{o u t}E S\ e r e r o}}\ {\ {(omega\_{z1})}}\\end{array} \\frac{1}{\\mathrm{r\_{C F}}C\_{\\mathrm{0T}}} \\frac{1}{\\mathrm{ _{C F}C_{\\mathrm{o U T}}}} \\frac{\\left(1-\\mathbf{D}\\right)^{2}}{\\mathbf{L}}\\left((\\mathbfmathbf{R} _{\\mathrm{O U T}}-\\frac{\\mathbf{r}_{\\mathrm{C F}},\\mathbf{R} _{\\mathrm{O U T}}}{\\mathbf{r}_{\\mathrm{C F}}+,\\mathbf{R} _{\\mathrm{O U T}}}\\right)-\\frac{\\mathbf{l}_{\\mathrm{L}}}{\\mathbf{L}} \\bar{\\mathfrak r e r0}\\left(\\omega\_{z2}\\right) \\frac{\\mathrm{R\_{O U T}}}{\\mathrm{M^{2}L}} \\frac{2}{\\mathrm{R\_{0U U}}}+\\frac{T\_{s}}{\\mathrm{L M^^{3}}}\\mathfrak{m\_{c}} (\\omega\_{p t}) (w\_{p i}) \\mathrm{C\_{O U T}} (\\omega\_{p2}) 2\\mathbf{F}\_{\\mathrm{S w}}\\Bigg(\\frac{1-\\frac{1}{\\mathbf{M}}}{\\mathbf{D}}\\Bigg)^{2} \\mathsf{P o l e}\\left(\\omega\_{n}\\right) \\mathcal{R} (boldsymbol Q{}\_{\\mathfrak{p}}) \\frac{1}{\\bf{S} _{n},m_{c},T\_{s}} \\frac{\\tri}{T\_{s}} \\pi\\big(\\mathfrak{m}\_{\\mathrm{c}}\\big(1-\ mathrm{D}),-,0.5\\big) 2\\bf{M},+,\\frac{R\_{O U T}T\_{s}}{L M^{2}}\\bigg(\\frac{1}{2},+,\\frac{S\_{a}}{S\_{n}}\\bigg) \\frac{2\\mathrm{V}\_{\\mathrm{O U T}}}{\\mathrm{ ~~D~~}}\\cdot\\frac{\\mathrm{M}-1}{2\\mathrm{M}-1} \\frac{\\mathrm{\\boldmath ~~\\cap~~ R}\_ _{mathrmmathrm{{O U T}}}}{\\mathrm{\\boldmath~R}_{i}} (H\_{c t r l\_o u t p u t}(t)) \\left11,+,\\mathrm{j},\\frac{2\\pi\\mathrm{f}}{00\_{z1}}\\right)\\left(1,-,\\mathrm{j},\\frac{2\\pi\\mathrm{f}}{00\_{z2}}\\right) \\left11;;+;\\mathrm{j},\\frac{2\\pi\\mathrm{f}}{\ {omega\_{{z}}}1}\\right)\\left11;;-\\;mathrm{{j j}},\\frac{2\\pi\\mathrm{f}}{{{\\omega}\_{{z}}}2}\\right) \\begin{array}{r}{{1}\\overline{{{\\left(1,+,j,{\\mathrm{{}}\ 2\\pi f}{{0mathrm{{}} _{p}}}\\right)\\left(1,+,j,{\\mathrm{{}}\ \\frac{2\\pi f,}{{{mathrm{{}}}_{0}\ {Q\_{p}}}+\\left(\\textstyle j,{\\frac{2\\pi f},{{{\\mathrm{{}}}\_{0}}}\\right)^{2}}}})}}}}}end{ * * * NCV8871 Table 2. FLYBACK CCM AND DCM TRANSFER FUNCTION EXPRESSIONS | | CCM | DCM | | --- | --- | --- | | Duty ratio(D) | $\\frac{V\_{OUT}}{V\_{OUT}+NV\_{IN}}$ | $\\frac{V\_{OUT}}{NV\_{IN}}\\sqrt{2\\tau\_{L}}$ | | Where:$\\tau\_{L}=\\frac{N^{2}L\_{p}}{T\_{s}R\_{OUT}}$ | | | | $V\_{OUT}/V\_{IN}$ DC Conversion Ratio(M) | $\\frac{N \\cdot D}{1-D}$ | $\\frac{N \\cdot D}{\\sqrt{2 \\cdot \\tau\_{L}}}$ | | Inductor On-slope($S\_{n}$),V/s | $\\frac{V\_{IN}}{L\_{p}}R\_{i}$ | $\\frac{V\_{IN}}{L\_{p}}R\_{i}$ | | Compensation Ramp($m\_{c}$) | $1+\\frac{S\_{a}}{S\_{n}}$ | $1+\\frac{S\_{a}}{S\_{n}}$ | | $C\_{\\text{out}}$ ESR Zero($\\omega\_{z1}$) | $\\frac{1}{r\_{\\text{CF}}C\_{\\text{OUT}}}$ | $\\frac{1}{r\_{\\text{CF}}C\_{\\text{OUT}}}$ | | Right-Half-Plane Zero($\\omega\_{z2}$) | $\\frac{(1-D)^{2}R\_{\\text{OUT}}}{D L\_{p} N^{2}}$ | $\\frac{R\_{\\text{OUT}}}{N^{2}L\_{p}}\\cdot\\frac{1}{M(M+1)}$ | | Modulator Pole($\\omega\_{p1}$) | $\\frac{\\frac{D^{\\prime 3}}{\\tau\_{L}}\\left(1+2\\frac{S\_{a}}{S\_{n}}\\right)+1+D}{R\_{\\text{OUT}}C\_{\\text{OUT}}}$ | $\\frac{2}{R\_{\\text{OUT}}C\_{\\text{OUT}}}$ | | $\\omega\_{p2}$ | - | $2F\_{\\text{SW}}\\left(\\frac{1}{D}\\frac{1}{M}\\right)^{2}$ | | $F\_{m}$ | $\\frac{1}{\\frac{D^{\\prime 2}}{\\tau\_{L}}\\left(1+2\\frac{S\_{a}}{S\_{n}}\\right)+2M+1}$ | $\\frac{1}{S\_{n}m\_{c}T\_{s}}$ | | $H\_{d}$ | $\\frac{R\_{\\text{OUT}}}{R\_{i}N}$ | $V\_{\\text{IN}}\\sqrt{\\frac{1}{2\\tau\_{L}}}$ | | Control-output Transfer Function($H\_{\\text{ctrl\_output}}(f)$) | $F\_{m}H\_{d}\\frac{\\left(1+j\\frac{2\\pi f}{\\omega\_{z1}}\\right)\\left(1-j\\frac{2\\pi f}{\\omega\_{z2}}\\right)}{\\left(1+j\\frac{2\\pi f}{\\omega\_{p1}}\\right)}$ | $F\_{m}H\_{d}\\frac{\\left(1+j\\frac{2\\pi f}{\\omega\_{z1}}\\right)\\left(1-j\\frac{2\\pi f}{\\omega\_{z2}}\\right)}{\\left(1+j\\frac{2\\pi f}{\\omega\_{p1}}\\right)}$ | \\mathrm{V}\_{\\mathrm{O U T}} \\frac{V\_{U T}}{N\\mathrm{{N}} _{mathrm N N}}\\sqrt{2\\mathfrak{t}_{\\mathrm L}} \\mathrm{V\_{O U T}+,\ N V\_{I N}} V\_{\\sf U U T}/N\_{\\sf N} \ {mathfrak r\_{\\mathrm{L}}}={\\frac{{bf N N}^{2},{\\bf L} _{\\mathrm{p}}}{{\\mathrm T}_{\\mathrm{s}},{\\bf R}\_{\\mathrm{O U T}}}} \\frac{\\mathrm{ ~~N~~}\\cdot\\mathrm{ ~~D~~}}{1-\\mathrm{ ~~D~~}} (s\_{n}) \\frac{\\mathrm{ ~~N~~}\\cdot\\mathrm{ ~~D~~}}{\\sqrt{2\\cdot\\tau\_{L}}} \\frac{\\sf{V} _{I N}}{\\sf{L}_{p}}{sf{R}\_{i}} \\frac{\\mathbf{V\_{I N}}}{\\mathbf{L\_{p}}}\\mathbf{R\_{i}} (m\_{c}) 1+\ \ \ {overline{{{sfsf}S}{}\_{\\mathrm{n}}}} \\mathrm{1 ~~+~~}frac S\_{a}}{S\_{n}} \\mathsf{C\_{o u t}E S R,Z e r o},(\\omega\_{z1}) \\frac{1}{{\ \ {\\mathrm{r}} _{\\mathrm{C F}}{\ {mathrm{C C}}_{\\mathrm{U T T}}}} \\frac{1}{\\mathbf{r\_{\\mathrm{C F}}}\\mathbf{C\_{\\mathrm{o U T}}}} \\left(1-\\mathbb{D}\\right)^{2}\\mathrm{R}\_{\ \ \\mathrm{0U T}} \\frac{\\mathrm{R} _{\\mathrm{O U T}}}{\\mathrm{N}^{2},\\mathrm{L}_{\\mathrm{p}}}\\cdot\\frac{1}{\\mathrm{M},(\\mathrm{M},+,1)} \\mathrm{{D},L\_{p}N^{2}} (\\omega\_{p t}) \ scriptstyle{\ frac{\\mathrm{D}{'}^{3}}{\\intercal{\\tt} _{L}}},(1;+;2\ {\\frac{\\mathrm{S}_{a}}{\\mathrm{S}\_{n}}});+;1;+;{\\bf D} \\frac{2}{\\mathrm{R\_{0mathrm{U T}}},\\mathrm{C\_{0\\mathrm{U T}}}} \\mathrm{R} _{\\mathrm{0U T}},\\mathrm{C}_{\\mathrm{0U U}} w\_{p2} 2\\mathbf{F}\_{\\mathrm{S W}}\\left(\\frac{\\frac{1}{\\mathbf{D}}}{1+\\frac{1}{\\mathbf{M}}}\\right)^{2} F\_{m} \ \\scriptstyle{frac{\ \\mathrm{D}^{\\prime}2}{\ \ _!{\\mathrm{L}}}},\\left(1,+,2,,{\\frac{\ \\mathrm{S}_{!mathrm{a}}}{\ \ \ \ \\\ \\\ }}\ \\right),+,2\\mathrm{\\bf{M}},+,1 \\frac{1}{{\\mathsf{S}} _{\\mathsf{n}},{\\mathsf{m}}_{\\mathsf{c}},{\\mathsf{T}}\_{\\mathsf{s}}} H\_{d} \\mathrm{R\_{O U T}} \\overline{{\\mathrm{V\_{\\mathrm{I N}},\\sqrt{\\frac{1}{2\\mathfrak{t}\_{\\mathrm{I}}}}}}} \\mathrm{F\_{m},\\mathrm{H\_{d}},\ }!(\\mathrm{\\frac{{1\ +\ j j\ {frac22pipi f}}{{0} _{z2}}}!\\left(\\mathrm\\middle-\ j\\frac{{\ 2\\pi f}}{{0}_{z2}}!\\right)}{!\\left(\\mathrm{1\ \ -\ j\ }frac{{22\\pipi}f}{{0}\_{z2}}!\\right)} \\mathrm{{\\left(1,+,i,j\\frac{2\\pi f}{{omega\_{z1}}}\\right)(\\hbar{-,,j,}frac2{pi}{{{\\omega}\_{z2}}})}} H\_{c t r l\_o u t p u t}(f) \\mathrm{F\_{m},H\_{d}\\frac{z\ \ r{\ \\\ \\\ z z\ {1,\ \ z\ \\\ \\\ \\\ \\\ \\\ \\\ \\\ \\\ \\\ \\\ \\\ \ \ component value adjustments may become necessary when R2 ≤ ~10·Resd as a result of approximations for determining components R2, C1, C2. R\_{2}\\leq{\\sim}10{\\cdot}R\_{e s d} R\_{2},C\_{l},C\_{2} * * * NCV8871 Table 3. OTA COMPENSATION TRANSFER FUNCTION AND COMPENSATION VALUES | Desired OTA Gain at Cross-over Frequency $f\_{c}(G)$ | $\\frac{desired\ G\_{c,w,e}}{10}\\frac{20}{1}$ | | --- | --- | | Desired Phase Boost at Cross-over Frequency $f\_{c}(\\text{boost})$ | $\\left(\\theta\_{\\text{margin}}-\\arg\\left(H\_{\\text{ctrl\_output}}\\left(f\_{c}\\right)\\right)\\frac{180^{\\circ}}{\\pi}-90^{\\circ}\\right)\\frac{\\pi}{180^{\\circ}}$ | | Select OTA Compensation Zero to Coincide with Modulator Pole at $f\_{p1}(f\_{z})$ | $\\frac{\\omega\_{p1e}}{2\\pi}$ | | Resulting OTA High Frequency Pole Placement ($f\_{p}$) | $\\frac{f\_{p}f\_{c}+f\_{c}^{2}\\tan(\\text{boost})}{f\_{c}-f\_{z}\\tan(\\text{boost})}$ | | Compensation Resistor $R\_{2}$ | $\\frac{f\_{p}G}{f\_{p}-f\_{z}}\\frac{V\_{\\text{OUT}}}{1.2g\_{m}}\\sqrt{1+\\left(\\frac{f\_{c}}{f\_{p}}\\right)^{2}}$ | | Compensation Capacitor $C\_{1}$ | $\\frac{1}{2\\pi f\_{p}G}\\cdot \\frac{R\_{\\text{low}}g\_{m}}{R\_{\\text{low}}+R\_{1}}$ | | OTA DC Gain($G\_{0,\\text{OTA}}$) | $\\frac{R\_{\\text{low}}}{R\_{\\text{low}}+R\_{1}}\\cdot g\_{m}\\cdot R\_{0}$ | | Low Frequency Zero($\\omega\_{z1e}$) | $\\frac{1}{2}\\frac{\\left(R\_{2}+R\_{\\text{esd}}\\right)}{R\_{2}R\_{\\text{esd}}C\_{2}}\\left\[1-\\sqrt{1-4\\frac{R\_{2}R\_{\\text{esd}}C\_{2}}{\\left(R\_{2}+R\_{\\text{esd}}\\right)^{2}C\_{1}}}\\right\]$ | | High Frequency Zero($\\omega\_{z2e}$) | $\\frac{1}{2}\\frac{\\left(R\_{2}+R\_{\\text{esd}}\\right)}{R\_{2}R\_{\\text{esd}}C\_{2}}\\left\[1+\\sqrt{1-4\\frac{R\_{2}R\_{\\text{esd}}C\_{2}}{\\left(R\_{2}+R\_{\\text{esd}}\\right)^{2}C\_{1}}}\\right\]$ | | Low Frequency Pole($\\omega\_{p1e}$) | $\\frac{1}{2}\\frac{\\left(R\_{0}+R\_{2}+R\_{\\text{esd}}\\right)}{R\_{2}\\left(R\_{0}+R\_{\\text{esd}}\\right)C\_{2}}\\left\[1-\\sqrt{1-4\\frac{R\_{2}\\left(R\_{0}+R\_{\\text{esd}}\\right)C\_{2}}{\\left(R\_{0}+R\_{2}+R\_{\\text{esd}}\\right)^{2}C\_{1}}}\\right\]$ | | High Frequency Pole($\\omega\_{p2e}$) | $\\frac{1}{2}\\frac{\\left(R\_{0}+R\_{2}+R\_{\\text{esd}}\\right)}{R\_{2}\\left(R\_{0}+R\_{\\text{esd}}\\right)C\_{2}}\\left\[1+\\sqrt{1-4\\frac{R\_{2}\\left(R\_{0}+R\_{\\text{esd}}\\right)C\_{2}}{\\left(R\_{0}+R\_{2}+R\_{\\text{esd}}\\right)^{2}C\_{1}}}\\right\]$ | | OTA Transfer Function($G\_{\\text{OTA}}(f)$) | -G0\_OTA $\\frac{\\left(1+j\\frac{2\\pi f}{\\omega\_{z1e}}\\right)}{\\left(1+j\\frac{2\\pi f}{\\omega\_{p1e}}\\right)}\\frac{\\left(1+j\\frac{2\\pi f}{\\omega\_{z2e}}\\right)}{\\left(1+j\\frac{2\\pi f}{\\omega\_{p2e}}\\right)}$ | t\_{c} \\mathbf{G}\_{\\mathrm{f c\_g a i n\_d b}} t\_{c} \\biggl(\\Theta\_{\\mathrm{m a r g i n}},-,\\mathrm{a r g\ }Bigl H{{\ H{}\_{c t r l\_o u t p u t}}(c)},),\\frac{180^{\\circ}}{\\pi},-,90^{\\circ},\\biggl)\\frac{\\pi}{180^{\\circ}} t\_{p1} \\frac{^{\\mathfrak{o o}}{\\mathtt{p l e}}}{2\\pi} (t\_{p}) \\mathrm{f\_{c}\ -\ f\_{Z}\\tan a((o o o t t)} R\_{Z} \\begin{array}{r l}{{}mathrm{}{}mathrm{} _{\\mathrm{f}{_}{\ _mathrm\\rho}G~}}&{{}\\mathrm{}\\mathrm{}\_\_{\\mathrm{O U T}}\ \\sqrt{1+\\left(\\frac{\\mathrm{f f_{c}}}{\\mathrm{f f\_{p}}}\\right)^{2}}}\\end{array} c\_{r} \\begin{array}{r}{\\overline{{\\mathrm{f\_{p}\ -\ f\_{z}}}}\ \ \\overline{{\ 1.2,g\_{m}}}\ \ {\\overline{{\\sqrt{1+\\left(\ {frac f\ f\_{z}{f\_{p}}}\\right)}}}}}\\end{array} c\_{R} \ \ {\\frac{1}{2\\pi,\\mathrm{f} _{z},\\mathrm{R}_{2}}} \\frac{1}{2\\pi,\\mathrm{f} _{\\mathrm{p}}\\mathrm{G}}\\cdot\\frac{\\mathrm{R}_{\\mathrm{l o w}},\\mathrm{g} _{\\mathrm{m}}}{\\mathrm{R}_{\\mathrm{l o w}}+,\\mathrm{R}\_{\\mathrm{1}}} (G\_{0},O T\_)A \\frac{\\sf{R} _{l\ w{}}}{\\sf{R}_{l o w},+, _{R_{1}}}\\cdot,\\sf{g} _{m},\\cdot,\\sf{R}_{0} (\\omega\_{z i e}) Low Voltage Operation If the input voltage drops below the UVLO or MOSFET \\frac{1}{2},\\frac{\\left(\\mathrm{}\ {bf R R} _{2},+,{mathrm{\\tiny{R}{_{e s d}}}}\\right)}{\\mathrm{}\ {}{\\bf R} _{2}{\\bf R}_{\\mathrm{s e d}}{\\bf C} _{2}}\\left\[1,-,\\sqrt{1-4\\frac{\\mathrm{}\ {}\ {mathrm\\tiny{R{R}{_{2}}\ }}\ {\\left\ \\mathrm{}{{} _{2}},\\mathrm{{\\tiny{R}{_{e s d}}}}\\right)}^{2}{mathrm}}\ {\\left{(\\bf}{\\mathrm{{R}{ _{2}}},+,{\\mathrm{\\tiny{R}{_{e s d}}}}\\right)}^{2}\\mathrm{}{}bf\\bar}}\ \ \\sf{T((f)=\ G\_{0A A}(f)H\_{c u l l\_o t t p l}(f)}\ \ If the input voltage drops below the UVLO or MOSFET\ threshold voltage, another voltage may be used to power the\ \ \\frac{1}{2},\\frac{\\left(\\mathrm{\ {}}\ \ \ \\\ (\\mathrm{{\ {R} _{0}+\\mathrm{{}\ }}}\\\mathrm{{{R}_{2}}}\ )\ {\\mathrm{{}}}\ \ \\frac{1}{2},\\frac{\\left(\\mathrm{R}{} _{0},+,\\mathrm{R}{{}_{2}},+,\\mathrm{R}{} _{\\mathrm{e s d}}\\right)}{\\mathrm{R}{}_{2}\\big(\\mathrm{R}{} _{0},+,\\mathrm{R}{}_{\\mathrm{e s d}}\\big} _{2},\\Bigg)\\left\\11,+,,\\sqrt{1-4\\frac{\\mathrm{R}{}_{2}\\big(\\mathrm{R}{{ _{0}}}+\\mathrm{R}{}_{\\mathrm{e s d}}\\big)\\mathrm{C} _{2}}{\\big(\\mathrm{R}{{{}_{0}}}+\\mathrm{R}{{{} _{2}}}+\\mathrm{R}{{{}_{\\mathrm{e s d}}}\\big)^{2}}\\mathrm{C}\_{1}},\\right}\ \ (\\up\_{O T A}()\ \ \\frac{-G\_{0\_O T A}\ \\ \ device. Simply connect the voltage you would like to boost\ to the inductor and connect the stable voltage to the VIN pin\ of the device. In boost configuration, the output of the\ converter can be used to power the device. In some cases it\ may be desirable to connect 2 sources to VIN pin, which can\ be accomplished simply by connecting each of the sources\ through a diode to the VIN pin.\ \ * * *\ \ SEPIC TOPOLOGY APPLICATION INFORMATION\ \ Figure 14. SEPIC Current Mode Schematic\ \ SEPIC Design Methodology\ This section details an overview of the component\ \ This section details an overview of the component\ selection process for the NCV8871 in continuous\ conduction mode SEPIC. It is intended to assist with the\ design process but does not remove all engineering design\ work. Many of the equations make heavy use of the small\ ripple approximation. This process entails the following\ steps:\ \ 01. Define Operational Parameters\ \ 02. Define Operational Parameters\ \ 03. Select Current Sense Resistor\ \ 04. Select Current Sense Resistor\ \ 05. Select SEPIC Inductors\ \ 06. Select SEPIC Inductors\ \ 07. Select Coupling Capacitor\ \ 08. Select Coupling Capacitor\ \ 09. Select Output Capacitors\ \ 10. Select Output Capacitors\ \ 11. Select Input Capacitors\ \ 12. Select Feedback Resistors\ \ 13. Select Output Capacitors\ \ 14. Select Input Capacitors\ \ 15. Select Input Capacitors\ \ 16. Select Feedback Resistors\ \ 17. Select Compensator Components\ \ 18. Select Compensator Components\ \ 19. Select MOSFET(s)\ \ 20. Define Operational Parameters\ \ 21. Select MOSFET(s)\ \ 22. Select Diode\ \ \ \\mathrm{D\_\_{m a x}}\ \ VIN(max): maximum input voltage \[V\]\ VOUT: output voltage \[V\]\ \ IOUT(max): maximum output current \[A\]\ ICL: desired typical cycle−by−cycle current limit \[A\]\ \ ICL: desired typical cycle−by−cycle current limit \[A\]\ \ VIN(min): minimum input voltage \[V\]\ VIN(max): maximum input voltage \[V\]\ \ \\mathrm{I\_{0U T(m a x)}}\ \ VOUT: output voltage \[V\]\ IOUT(max): maximum output current \[A\]\ \ From this the ideal minimum and maximum duty cycles\ can be calculated as follows:\ \ \\mathsf{D}{ _{\\mathsf{m i n}}}=\\frac{\\mathsf{V}_{\\mathsf{O0T}}}{\\mathsf{V} _{\\mathsf{I N(m a x)}}+\\mathsf{V}_{\\mathsf{O U T}}}\ \ \\mathsf{D}{ _{\\mathsf{m a x}}}=\\frac{\\mathsf{V}_{\\mathsf{O U T}}}{\\mathsf{V} _{\\mathsf{I N(n i n)}}+\\mathsf{V}_{\\mathsf{O U T}}}\ \ Both duty cycles will actually be higher due to power loss\ in the conversion. The exact duty cycles will depend on\ conduction and switching losses.\ If the calculated D (worst case) is higher than the D\ \ If the calculated DWC (worst case) is higher than the Dmax\ limit of the NCV8871, the conversion will not be possible.\ It is important for a SEPIC converter to have a restricted\ Dmax, because while the ideal conversion ratio of a SEPIC\ converter goes up to infinity as D approaches 1, a real\ converter’s conversion ratio starts to decrease as losses\ overtake the increased power transfer. If the converter is in\ this range it will not be able to regulate properly.\ If the following equation is not satisfied, the device will\ \ \\mathrm{D\_{m a x}}\ \ If the following equation is not satisfied, the device will\ skip pulses at high VIN:\ D\ \ \\mathrm{V\_{N Nmathrm}}}\ \ \\frac{\\mathsf{D} _{\\mathsf{m i n}}}{f_{\\mathsf{s}}}\\geq t\_{\\mathsf{o n m m()))}}\ \ Where: f : switching frequency \[Hz\]s\ ton(min): minimum on time \[s\]\ \ * * *\ \ 2. Select Current Sense Resistor\ Current sensing for peak current mode control and current\ \ Current sensing for peak current mode control and current\ limit relies on the MOSFET current signal, which is\ measured with a ground referenced amplifier. Note that the\ ICL equals the sum of the currents from both inductors. The\ easiest method of generating this signal is to use a current\ sense resistor from the source of the MOSFET to device\ ground. The sense resistor should be selected as follows:\ V\ \ \\mathrm{I\_{C L}}\ \ \\mathsf{R\_{S}}=\\frac{\\mathsf{V\_{C L}}}{\\mathsf{I\_{C L}}}\ \ Where: RS: sense resistor \[\]\ VCL: current limit threshold voltage \[V\]\ \ VCL: current limit threshold voltage \[V\]\ ICL: desire current limit \[A\]\ \ ICL: desire current limit \[A\]\ \ \\mathrm{I}\_{\\mathrm{C L}}\ \ 3. Select SEPIC Inductors\ The output inductor controls the current ripple that occurs\ \ The output inductor controls the current ripple that occurs\ over a switching period. A high current ripple will result in\ excessive power loss and ripple current requirements. A low\ current ripple will result in a poor control signal and a slow\ current slew rate in case of load steps. A good starting point\ for peak to peak ripple is around 20−40% of the inductor\ current at the maximum load at the worst case VIN, but\ operation should be verified empirically. The worst case VIN\ is the minimum input voltage. After choosing a peak current\ ripple value, calculate the inductor value as follows:\ V D\ \ \\mathrm{V N},\ \ \\mathsf{L}=\\frac{\\mathsf{V} _{\\mathsf{I N(W C)}}\\mathsf{D}_{\\mathsf{W C}}}{\\Delta\\mathsf{I} _{\\mathsf{L,m a x}}f_{\\mathsf{s}}}\ \ Where: VIN(WC): VIN value as close as possible to half of\ VOUT \[V\]\ DWC: duty cycle at VIN(WC)\ \ \\mathrm{V\_{I N(W C)}:V\_{I N}}\ \ DWC: duty cycle at VIN(WC)\ IL,max: maximum peak to peak ripple \[A\]\ \ IL,max: maximum peak to peak ripple \[A\]\ The maximum average inductor current can be calculated as\ \ \\mathrm{V}{}\_{\\mathrm{I N}(\\mathrm{W C})}\ \ {mathfrak C C}.\ \ \\Delta\\mathrm{I}\_{\\mathrm{L}m a x}\ \ The maximum average inductor current can be calculated as\ follows:\ V I\ \ 4. Select Coupling Capacitor\ Coupling capacitor RMS current is significant. A low\ ESR ceramic capacitor is required as a coupling capacitor.\ Selecting a capacitor value too low will result in high\ capacitor ripple voltage which will distort ripple current and\ diminish input line regulation capability. Budgeting 2−5%\ coupling capacitor ripple voltage is a reasonable guideline.\ I D\ \ \\mathsf{I} _{\\mathsf{L},\\mathsf{A V G}}=\\frac{\\mathsf{V}_{\\mathsf{O U T}}\\mathsf{I} _{\\mathsf{O U T}m a x})}{\\mathsf{V}_{\\mathsf{I N}(\\mathsf{m i n})}\\mathsf{n}}\ \ The Peak Inductor current can be calculated as follows:\ \ \\mathsf{I}{} _{\\mathsf{L2,p e a k}}=\\mathsf{I}_{\\mathsf{O U T(m a x)}}+\\frac{\\Delta\\mathsf{I}\_{\\mathsf{L2}}}{2}\ \ 4. Select Coupling Capacitor\ Coupling capacitor RMS current is significant. A low\ \ Where (if L1 = L2): IL1 = IL2\ \ \\mathsf\_{L1,p e a k}=\\mathsf I\_{L1,a v g}+\\frac{\\Delta\\mathsf I\_{L1}}{2}\ \ f\_{\\sf r e s o n a n c e}=\\frac{1}{2\\pi\\sqrt{(L1+L2)C\_{\\sf c o u p l i n g}}}\ \ Current mode control helps resolve some of the resonant\ frequencies that create issues in voltage mode SEPIC\ converter designs, but some resonance issues may occur. A\ resonant frequency exists at\ \ It may become necessary to place an RC damping network\ in parallel with the coupling capacitor if the resonance is\ within ~1 decade of the closed−loop crossover frequency.\ The capacitance of the damping capacitor should be ~5\ times that of the coupling capacitor. The optimal damping\ resistance (including the ESR of the damping capacitor) is\ calculated as\ \ \\mathsf{R} _{\\tt d a m p i n g}=\\sqrt{\\frac{L1+L2}{C_{\\tt c o u p l i n g}}}\ \ The output capacitors smooth the output voltage and\ reduce the overshoot and undershoot associated with line\ transients. The steady state output ripple associated with the\ output capacitors can be calculated as follows:\ \ The capacitors need to survive an RMS ripple current as\ follows:\ \ \\mathbf{V}\_{\\mathrm{r e f}}.\ \ 1sf\_{C o u t(R M S)}=\\sqrt{1sf/ _{{O U T(m a x)}}^{2}D\_{W C}+\\left(I{a}^{2}+\\frac{I_{r}^{2}}{3}-I\_{a}I\_{r}\\right)D\_{W C}^{\\prime}}\ \ I\_{\\sf{a}}=I\_{\\sf{L1p\_a e a k}}+I\_{\\sf{L2\ _e a a k}}-I_{\\sf{o u t}}\ \ The use of parallel ceramic bypass capacitors is strongly\ encouraged to help with the transient response.\ \ \\mathsf\_{\\mathsf{r}}=\\Delta\\mathsf{I} _{\\mathsf{L}1}+\\Delta\\mathsf{I}_{\\mathsf{L}2}\ \ The input capacitor reduces voltage ripple on the input to\ the module associated with the ac component of the input\ current.\ I\ \ \\mathsf{R} _{\\mathsf{u p p e r}}=\\mathsf{R}_{\\mathsf{l o w e r}}\\frac{\\left((mathsfmathsf V V\_{\\mathsf{o u t}}-\\mathsf V\_{\\mathsf{r e f}}\\right\ )}{\\mathsf V\_{\\mathsf{r e f}}}\ \ * * *\ \ NCV8871\ \ The total feedback resistance (Rupper + Rlower) should be\ in the range of 1 k – 100 k.\ \ (\\mathrm{R} _{\\tt{u p p e r}}+\\mathrm{R}_{\\tt{l o w e r}})\ \ 8. Select Compensator Components\ Current Mode control method employed by the\ \ Current Mode control method employed by the\ NCV8871 allows the use of a simple, Type II compensation\ to optimize the dynamic response according to system\ requirements.\ \ 9. Select MOSFET(s)\ In order to ensure the gate drive voltage does not drop out\ \ In order to ensure the gate drive voltage does not drop out\ the MOSFET(s) chosen must not violate the following\ inequality:\ I\ \ \\mathsf{Q} _{\\mathsf{g(t o t a l)}}\\leq\\frac{\\mathsf{I}_{\\mathsf{d n}}}{f\_{\\mathsf{S}}}\ \ Where: Qg(total): Total Gate Charge of MOSFET(s) \[C\]\ Idrv: Drive voltage current \[A\]\ fs: Switching Frequency \[Hz\]\ \ \\mathrm{Q\_{g(t o t a l)}}.\ \ \\mathrm{I}\_{\\mathrm{d r v}}\ \ The maximum RMS Current can be calculated as follows:\ \ \\mathbf{f}\_{\\mathrm{s}}.\ \ \ _{\\sf{D(a a a)}},=,\\sqrt{\\sf{D}_{W\ !!G}\\Bigg(\ 1\\sb\_{Q(!a a l)},^{2}+\\frac{\\big(\\Delta\\sf{I} _{L1},+,\\Delta\\sf{I}_{L2}\\big)^{2}}{3}-1\ {\\sf I} _{Q\ p!a c a l l}\\big(\\Delta\\sf{I}_{L1},+,\\Delta\\sf{I}\_{L2}\\big)\\Bigg)}.\ \ where\ \ \\mathsf{V} _{\\mathsf{O0m m a}}=\\mathsf{V}_{\\mathsf{O U T(m a x)}}+\\mathsf{V}\_{\\mathsf{I N(m a x)}}\ \ C(D e a H)==I\_{L1\_e e a}+I\_{L2\_\_a e a k}\ \ The maximum voltage across the MOSFET will be the\ maximum output voltage, which is the higher of the\ maximum input voltage and the regulated output voltaged:\ \ * * *\ \ SOIC−8 NB\ CASE 751−07\ ISSUE AK\ \ NOTES:\ \ 1. DIMENSIONING AND TOLERANCING PER\ \ NOTES:\ \ 1. DIMENSIONING AND TOLERANCING PER\ ANSI Y14.5M, 1982.\ 2. CONTROLLING DIMENSION: MILLIMETER.\ \ ANSI Y14.5M, 1982.\ 2\. CONTROLLING DIMENSION: MILLIMETER.\ 3\. DIMENSION A AND B DO NOT INCLUDE\ \ 2. CONTROLLING DIMENSION: MILLIMETER.\ 3. DIMENSION A AND B DO NOT INCLUDE\ MOLD PROTRUSION.\ 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)\ \ MAXIMUM MATERIAL CONDITION.\ 6\. 751−01 THRU 751−06 ARE OBSOLETE. NEW\ STANDARD IS 751−07.\ \ PER SIDE.\ 5\. DIMENSION D DOES NOT INCLUDE DAMBAR\ PROTRUSION. ALLOWABLE DAMBAR\ PROTRUSION SHALL BE 0.127 (0.005) TOTAL\ IN EXCESS OF THE D DIMENSION AT\ MAXIMUM MATERIAL CONDITION.\ 6\. 751−01 THRU 751−06 ARE OBSOLETE. NEW\ \ SOLDERING FOOTPRINT\*\ \ MOLD PROTRUSION.\ 4\. MAXIMUM MOLD PROTRUSION 0.15 (0.006)\ PER SIDE.\ 5\. DIMENSION D DOES NOT INCLUDE DAMBAR\ \ | DIM | MILLIMETERS | | INCHES | |\ | --- | --- | --- | --- | --- |\ | MIN | MAX | MIN | MAX | |\ | A | 4.80 | 5.00 | 0.189 | 0.197 |\ | B | 3.80 | 4.00 | 0.150 | 0.157 |\ | C | 1.35 | 1.75 | 0.053 | 0.069 |\ | D | 0.33 | 0.51 | 0.013 | 0.020 |\ | G | 1.27 BSC | | 0.050 BSC | |\ | H | 0.10 | 0.25 | 0.004 | 0.010 |\ | J | 0.19 | 0.25 | 0.007 | 0.010 |\ | K | 0.40 | 1.27 | 0.016 | 0.050 |\ | M | 0° | 8° | 0° | 8° |\ | N | 0.25 | 0.50 | 0.010 | 0.020 |\ | S | 5.80 | 6.20 | 0.228 | 0.244 |\ \ GENERIC\ MARKING DIAGRAM\*\ \ DOCUMENT NUMBER: 98ASB42564B\ \ \*For additional information on our Pb−Free strategy and soldering\ details, please download the onsemi Soldering and Mounting\ Techniques Reference Manual, SOLDERRM/D.\ \ IC\ (Pb−Free)\ \ | DOCUMENT NUMBER: | 98ASB42564B | Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped“CONTROLLED COPY”in red. | |\ | --- | --- | --- | --- |\ | DESCRIPTION: | SOIC-8 NB | | PAGE 1 OF 2 |\ \ DESCRIPTION: SOIC−8 NB\ \ Electronic versions are uncontrolled except when accessed directly from the Document Repository.\ Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.\ \ XXXXX = Specific Device Code\ A = Assembly Location\ L = Wafer Lot\ \ A = Assembly Location\ Y = Year\ \ L = Wafer Lot\ Y = Year\ \ STYLES ON PAGE 2\ \ Y = Year\ W = Work Week\ = Pb−Free Package\ \ Y = Year\ WW = Work Week\ \ WW = Work Week\ = Pb−Free Package\ \ onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves\ the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular\ purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation\ special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.\ \ = Pb−Free Package\ \ ^\\mathrm{i l}\\mathrm{G}^{\\mathrm{i l}}\ \ * * *\ \ SOIC−8 NB\ CASE 751−07\ ISSUE AK\ \ STYLE 1:\ PIN 1. EMITTER\ 2\. COLLECTOR\ 3\. COLLECTOR\ 4\. EMITTER\ 5\. EMITTER\ 6\. BASE\ 7\. BASE\ 8\. EMITTER\ STYLE 5:\ PIN 1. DRAIN\ 2\. DRAIN\ 3\. DRAIN\ 4\. DRAIN\ 5\. GATE\ 6\. GATE\ 7\. SOURCE\ 8\. SOURCE\ STYLE 9:\ PIN 1. EMITTER, COMMON\ 2\. COLLECTOR, DIE #1\ 3\. COLLECTOR, DIE #2\ 4\. EMITTER, COMMON\ 5\. EMITTER, COMMON\ 6\. BASE, DIE #2\ 7\. BASE, DIE #1\ 8\. EMITTER, COMMON\ STYLE 13:\ PIN 1. N.C.\ 2\. SOURCE\ 3\. SOURCE\ 4\. GATE\ 5\. DRAIN\ 6\. DRAIN\ 7\. DRAIN\ 8\. DRAIN\ STYLE 17:\ PIN 1. VCC\ 2\. V2OUT\ 3\. V1OUT\ 4\. TXE\ 5\. RXE\ 6\. VEE\ 7\. GND\ 8\. ACC\ STYLE 21:\ PIN 1. CATHODE 1\ 2\. CATHODE 2\ 3\. CATHODE 3\ 4\. CATHODE 4\ 5\. CATHODE 5\ 6\. COMMON ANODE\ 7\. COMMON ANODE\ 8\. CATHODE 6\ STYLE 25:\ PIN 1. VIN\ 2\. N/C\ 3\. REXT\ 4\. GND\ 5\. IOUT\ 6\. IOUT\ 7\. IOUT\ 8\. IOUT\ STYLE 29:\ PIN 1. BASE, DIE #1\ 2\. EMITTER, #1\ 3\. BASE, #2\ 4\. EMITTER, #2\ 5\. COLLECTOR, #2\ 6\. COLLECTOR, #2\ 7\. COLLECTOR, #1\ 8\. COLLECTOR, #1\ \ STYLE 2:\ PIN 1. COLLECTOR, DIE, #1\ 2\. COLLECTOR, #1\ 3\. COLLECTOR, #2\ 4\. COLLECTOR, #2\ 5\. BASE, #2\ 6\. EMITTER, #2\ 7\. BASE, #1\ 8\. EMITTER, #1\ STYLE 6:\ PIN 1. SOURCE\ 2\. DRAIN\ 3\. DRAIN\ 4\. SOURCE\ 5\. SOURCE\ 6\. GATE\ 7\. GATE\ 8\. SOURCE\ STYLE 10:\ PIN 1. GROUND\ 2\. BIAS 1\ 3\. OUTPUT\ 4\. GROUND\ 5\. GROUND\ 6\. BIAS 2\ 7\. INPUT\ 8\. GROUND\ STYLE 14:\ PIN 1. N−SOURCE\ 2\. N−GATE\ 3\. P−SOURCE\ 4\. P−GATE\ 5\. P−DRAIN\ 6\. P−DRAIN\ 7\. N−DRAIN\ 8\. N−DRAIN\ STYLE 18:\ PIN 1. ANODE\ 2\. ANODE\ 3\. SOURCE\ 4\. GATE\ 5\. DRAIN\ 6\. DRAIN\ 7\. CATHODE\ 8\. CATHODE\ STYLE 22:\ PIN 1. I/O LINE 1\ 2\. COMMON CATHODE/VCC\ 3\. COMMON CATHODE/VCC\ 4\. I/O LINE 3\ 5\. COMMON ANODE/GND\ 6\. I/O LINE 4\ 7\. I/O LINE 5\ 8\. COMMON ANODE/GND\ STYLE 26:\ PIN 1. GND\ 2\. dv/dt\ 3\. ENABLE\ 4\. ILIMIT\ 5\. SOURCE\ 6\. SOURCE\ 7\. SOURCE\ 8\. VCC\ STYLE 30:\ PIN 1. DRAIN 1\ 2\. DRAIN 1\ 3\. GATE 2\ 4\. SOURCE 2\ 5\. SOURCE 1/DRAIN 2\ 6\. SOURCE 1/DRAIN 2\ 7\. SOURCE 1/DRAIN 2\ 8\. GATE 1\ \ STYLE 3:\ PIN 1. DRAIN, DIE #1\ 2\. DRAIN, #1\ 3\. DRAIN, #2\ 4\. DRAIN, #2\ 5\. GATE, #2\ 6\. SOURCE, #2\ 7\. GATE, #1\ 8\. SOURCE, #1\ STYLE 7:\ PIN 1. INPUT\ 2\. EXTERNAL BYPASS\ 3\. THIRD STAGE SOURCE\ 4\. GROUND\ 5\. DRAIN\ 6\. GATE 3\ 7\. SECOND STAGE Vd\ 8\. FIRST STAGE Vd\ STYLE 11:\ PIN 1. SOURCE 1\ 2\. GATE 1\ 3\. SOURCE 2\ 4\. GATE 2\ 5\. DRAIN 2\ 6\. DRAIN 2\ 7\. DRAIN 1\ 8\. DRAIN 1\ STYLE 15:\ PIN 1. ANODE 1\ 2\. ANODE 1\ 3\. ANODE 1\ 4\. ANODE 1\ 5\. CATHODE, COMMON\ 6\. CATHODE, COMMON\ 7\. CATHODE, COMMON\ 8\. CATHODE, COMMON\ STYLE 19:\ PIN 1. SOURCE 1\ 2\. GATE 1\ 3\. SOURCE 2\ 4\. GATE 2\ 5\. DRAIN 2\ 6\. MIRROR 2\ 7\. DRAIN 1\ 8\. MIRROR 1\ STYLE 23:\ PIN 1. LINE 1 IN\ 2\. COMMON ANODE/GND\ 3\. COMMON ANODE/GND\ 4\. LINE 2 IN\ 5\. LINE 2 OUT\ 6\. COMMON ANODE/GND\ 7\. COMMON ANODE/GND\ 8\. LINE 1 OUT\ STYLE 27:\ PIN 1. ILIMIT\ 2\. OVLO\ 3\. UVLO\ 4\. INPUT+\ 5\. SOURCE\ 6\. SOURCE\ 7\. SOURCE\ 8\. DRAIN\ \ STYLE 4:\ PIN 1. ANODE\ 2\. ANODE\ 3\. ANODE\ 4\. ANODE\ 5\. ANODE\ 6\. ANODE\ 7\. ANODE\ 8\. COMMON CATHODE\ STYLE 8:\ PIN 1. COLLECTOR, DIE #1\ 2\. BASE, #1\ 3\. BASE, #2\ 4\. COLLECTOR, #2\ 5\. COLLECTOR, #2\ 6\. EMITTER, #2\ 7\. EMITTER, #1\ 8\. COLLECTOR, #1\ STYLE 12:\ PIN 1. SOURCE\ 2\. SOURCE\ 3\. SOURCE\ 4\. GATE\ 5\. DRAIN\ 6\. DRAIN\ 7\. DRAIN\ 8\. DRAIN\ STYLE 16:\ PIN 1. EMITTER, DIE #1\ 2\. BASE, DIE #1\ 3\. EMITTER, DIE #2\ 4\. BASE, DIE #2\ 5\. COLLECTOR, DIE #2\ 6\. COLLECTOR, DIE #2\ 7\. COLLECTOR, DIE #1\ 8\. COLLECTOR, DIE #1\ STYLE 20:\ PIN 1. SOURCE (N)\ 2\. GATE (N)\ 3\. SOURCE (P)\ 4\. GATE (P)\ 5\. DRAIN\ 6\. DRAIN\ 7\. DRAIN\ 8\. DRAIN\ STYLE 24:\ PIN 1. BASE\ 2\. EMITTER\ 3\. COLLECTOR/ANODE\ 4\. COLLECTOR/ANODE\ 5\. CATHODE\ 6\. CATHODE\ 7\. COLLECTOR/ANODE\ 8\. COLLECTOR/ANODE\ STYLE 28:\ PIN 1. SW\_TO\_GND\ 2\. DASIC\_OFF\ 3\. DASIC\_SW\_DET\ 4\. GND\ 5\. V\_MON\ 6\. VBULK\ 7\. VBULK\ 8\. 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